Verilog jobs - Santa Clara, CA
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| Jul 29 | Intern | Broadcom | Sunnyvale, CA |
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required, MSEE preferred. Experience with verilog and digital design is a must. Experience with encryption algorithms preferred. more |
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| Jul 29 | Intern II | Broadcom | Sunnyvale, CA |
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I Development of cryptographic accleration engines for cellular baseband ASICs. Job Requirements BSEE required, MSEE preferred.Experience with verilog and digital design is a... more |
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| Jul 29 | Engineer, Sr Staff - IC Design | Broadcom | San Jose, CA |
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implementing testplans, developing System Verilog tests and checkers, creating ... Verilog or Vera -- Familiar with System Verilog Assertions -- Strong experience in... more |
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| Jul 29 | Engineer, Sr Staff - IC Design II | Broadcom | San Jose, CA |
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ong experience on class of service, large number of queuing scheduling and multi-layer traffic management experience is a plus- Familiar with Verilog/System Verilog- Must be... more |
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| Jul 29 | Intern | Broadcom | Sunnyvale, CA |
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Proficiency in VHDL/Verilog, and experience in C/C++, PERL., and TCL. A solid understanding of digital design, communication theory for WCDMA/CDMA, VLSI design and familiarity... more |
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| Jul 29 | Engineer, Sr Staff - IC Design | Broadcom | San Jose, CA |
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implementing testplans, developing System Verilog tests and checkers, creating ... Verilog or Vera-- Familiar with System Verilog Assertions-- Strong experience in... more |
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| Jul 29 | Engineer, Staff Design | Marvell Technology Group | Santa Clara, CA |
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hands-on using design tools such as Spice, Verilog, DC-Compiler and Matlab to achieve design requirements. Knowledge/experience on design flow from concept to silicon is... more |
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| Jul 29 | Intern | Broadcom | Sunnyvale, CA |
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Proficiency in VHDL/Verilog, and experience in C/C++, PERL., and TCL. A solid understanding of digital design, communication theory for WCDMA/CDMA, VLSI design and familiarity... more |
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| Jul 29 | Intern II | Broadcom | San Jose, CA |
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Excellent communication skills Knowledge of Verilog or VHDL design languages is a must Experience in digital logic design and verification is a must FPGA synthesis experience is a... more |
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| Jul 29 | SoC VERIFICATION LEAD/MANAGER | Scintera | Sunnyvale, CA |
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Fluent in HDL modeling languages such as Verilog and SystemVerilog Fluency in Matlab and C programming is a plus Need to be "hands on" - this position requires a lot of technical... more |
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| Jul 29 | Pre-Si Design Automation Engineer | Intel | Santa Clara, CA |
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for RTL Verification including verilog simulation with VCS, SystemVerilog Testbench/OVM, and/or expertise with Formal Property Verification. - 8+ years experience with RTL... more |
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| Jul 29 | Sr. Verification Engineer(Ethernet, C++) | Synapse Design Automation | San Jose, CA |
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Verilog, c/c++, perl mandatory both directed and randomized tests for complex systems coverage analysis and testplan development needed Hands-on, recent experience with... more |
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| Jul 29 | Engineer, Sr Staff - IC Design | Broadcom | Santa Clara, CA |
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to the ASIC development process including Verilog, VHDL, Unix Scripting, and C. Working experience needs to demonstrate the technical expertise in successful completion of... more |
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| Jul 29 | Engineer, Staff II - IC Design Verification | Broadcom | Sunnyvale, CA |
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Proficiency in VHDL/Verilog, and experience in C/C++, PERL., and TCL. A solid understanding of digital design, communication theory for WCDMA/CDMA, VLSI design and familiarity... more |
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| Jul 29 | Design Engineer | SanDisk | Milpitas, CA |
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4) MOS VLSI circuit design, 5) SPICE/Verilog simulator, 6) static memory, 7) logic design. SanDisk offers a highly competitive compensation package and great benefits, which... more |
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| Jul 29 | SR. Verification Engineer | Synapse Design Automation | San Jose, CA |
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and high level languages (HVL) like System Verilog, Vera or Specman e Create test plans ... verification Create assertions with System Verilog and verify using static tools or... more |
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| Jul 29 | Design Engineer | SanDisk | Milpitas, CA |
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1) numerical circuit analysis, 2) Verilog, 3) electronic devices, 4) logic design, 5) digital IC design and layout experience, 6) analog IC design, 7) SPICE, and 8) computer... more |
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| Jul 29 | Verification Engineer | Korcomptenz | Milpitas, CA |
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in developing system level test cases in verilog and C, with PSL assertions*Experience with and thorough understanding of SOC simulation and verification methodology, tools, and... more |
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| Jul 29 | Sr. DFT engineer | Synapse Design Automation | San Jose, CA |
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C++, Perl, tcl, make, Linux/Unix shell script. - Proficiency in analyzing reports from DFT and STA tools. - Proficiency in logic design,Verilog coding and analysis. - Good... more |
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| Jul 28 | Sr. ASIC Verification Engineer | Dynamic Staffing | Santa Clara, CA |
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with Verilog, SystemVerilog and System Verilog Assertions Familiarity with ... Keywords: ASIC Design ASIC verification Verilog RTL test plans test-bench... more |
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| Jul 28 | Intern | Broadcom | Sunnyvale, CA |
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required, MSEE preferred. Experience with verilog and digital design is a must. Experience with encryption algorithms preferred. Country United States State/Province California... more |
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| Jul 28 | Digital Design Engineer - ASIC Design - IC Designer - RTL - Verilog - CMOS Image Sensors | Cybercoders | Palo Alto, CA |
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- ASIC Design - IC Designer - RTL - Verilog - CMOS Image Sensors Required Skills ... asic, cmos, cis, imaging, image sensors, verilog, image processing, graphics,... more |
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| Jul 28 | Engineer, Sr Staff - IC Design | Broadcom | San Jose, CA |
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implementing testplans, developing System Verilog tests and checkers, creating ... Verilog or Vera -- Familiar with System Verilog Assertions -- Strong experience in... more |
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| Jul 28 | Intern | Broadcom | Sunnyvale, CA |
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Proficiency in VHDL/Verilog, and experience in C/C++, PERL., and TCL. A solid understanding of digital design, communication theory for WCDMA/CDMA, VLSI design and familiarity... more |
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| Jul 28 | Application Engineer ? Signal Integrity (Repeaters/Re-timer | IDT | San Jose, CA |
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that are considered a definite plus:Matlab, Verilog-A, protocol expertise in PCIe Gen3, SRIO 2.0, USB3.0, etc highly desirable; past experience with Compliance Testing of these or... more |
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| Jul 27 | Design Engineer, MTS | Altera | San Jose, CA |
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with a strong background in RTL design, Verilog/VHDL knowledge. Good understanding of software programming principles including proficiency in C/C++ is expected. Some... more |
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| Jul 27 | Senior PreSi Verification Eng | Intel | Santa Clara, CA |
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ModelSim*, coverage analysis, VHDL and/or Verilog*, C , and Perl scripting is also ... - Experience with System Verilog is a must - Experience with complex SoC Design and... more |
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| Jul 27 | Pre-Si Validation Engineer | Intel | Santa Clara, CA |
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of uArchitecture, proficiency in System Verilog, VCS, Specman and scripting - Experience in validation test environment, test automation, test content, coverage and enabling... more |
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| Jul 27 | Pre-Si Validation Engineer | Intel | Santa Clara, CA |
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of uArchitecture, proficiency in System Verilog, VCS, Specman and scripting - Experience in validation test environment, test automation, test content, coverage and enabling... more |
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| Jul 27 | Pre-Si Validation Engineer | Intel | Santa Clara, CA |
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of uArchitecture, proficiency in System Verilog, VCS, Specman and scripting - Experience in validation test environment, test automation, test content, coverage and enabling... more |
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| Jul 27 | Hardware Verification Engineer | S & A Associates | San Jose, CA |
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ASIC and FPGA verification in a System Verilog and Verilog based environment ... test benches Strong programming skills in Verilog and System Verilog required. more |
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| Jul 27 | Design Engineer - Senior - Analog/Mixed Signal | Intersil | Milpitas, CA |
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state-machines, I2C bus interfaces) and Verilog knowledge. (c) Experience at designing system level IC as well as Subthreshold CMOS design. Advanced understanding of layout... more |
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| Jul 27 | ASIC/FPGA Design Engineer | Cisco Systems | San Jose, CA |
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and ASIC designs, and fluency in System Verilog/Verilog language. Experience with C/C++ or scripting languages (PERL, shell) is a plus as is knowledge of basic networking... more |
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| Jul 27 | Design Engineer | Kawasaki Microelectronics America | San Jose, CA |
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design and development including coding in Verilog/VHDL & simulation; perform digital ... with: high-speed digital VLSI design; RTL verilog, low power design and ability to... more |
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| Jul 27 | VLSI Design Engineer - Video | Zoran | Sunnyvale, CA |
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in one of following areas such as video capture, de-interlacing, noise reduction, scaling and display functions. Programming: Proficient in Verilog, C, Unix shell scripting,... more |
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| Jul 27 | ASIC Design Engineer | Terran Systems | San Jose, CA |
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success. A strong understanding of verilog RTL, experiences in Cadence andprimetime Understanding of deep-submicron effects as related to SI & DFM are highlydesirable. Strong... more |
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| Jul 27 | ENGINEER.II.ASIC DEVELOPER ENGINEER | Cisco Systems | San Jose, CA |
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tools, scripting and programming languages (verilog, SV, C++, Perl, etc.). - Good problem solving skills. - Good communication skills and a team player. - Networking knowledge... more |
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| Jul 27 | Staff Verification Engineer | Actel | Mountain View, CA |
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in the following HDL languages System Verilog, Verilog and VHDL Good knowledge of UNIX shell scripting , Perl and TCL scripting Good knowledge and understanding of CMOS device... more |
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| Jul 27 | Post-silicon Validation and Embedded System Engineer | Zoran | Sunnyvale, CA |
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trong background in HW development, design and debugging and knowledge of HW debugging tools Extensive (minimum of 2 years) hands-on experience in RTL programming (Verilog) in... more |
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| Jul 26 | Digital Design Engineer - ASIC Design - IC Designer - RTL - CIS | Cybercoders | Palo Alto, CA |
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sensors - Experience with RTL coding in Verilog, verification, validation, ... asic, cmos, cis, imaging, image sensors, verilog, image processing, graphics,... more |
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| Jul 26 | Design Engineer | SanDisk | Milpitas, CA |
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4) MOS VLSI circuit design, 5) SPICE/Verilog simulator, 6) static memory, 7) logic design. SanDisk offers a highly competitive compensation package and great benefits, which... more |
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| Jul 26 | Senior Logic Design Engineer - Digital Design Engineer | Cybercoders | Milpitas, CA |
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experience in Asynchronous Logic Design, Verilog, and Analog or Mixed-Signal ... , Asynchronous, Mixed Signal, Analog, Verilog, Schematic Capture, Spice... more |
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| Jul 26 | Senior DFT Engineer - Design For Test | Cybercoders | Cupertino, CA |
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- Strong experience in Logic Design, Verilog RTL, Verification, and Static Timing ... JTAG, Scan Insertion, ATPG, Logic Design, Verilog RTL, Verification, STA, Boundary... more |
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| Jul 26 | Design Engineer, MTS | Altera | San Jose, CA |
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with a strong background in RTL design, Verilog/VHDL knowledge. ? Good understanding of software programming principles including proficiency in C/C++ is expected. ? Some... more |
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| Jul 26 | ASIC Design Engineer - US (Job Code:ASIC-D-US) | Infinera | Sunnyvale, CA |
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level specification, micro- architecture, Verilog RTL design, verification and ... with standard ASIC design flow including Verilog simulators, synthesis, Timing... more |
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| Jul 26 | Design Engineer | SanDisk | Milpitas, CA |
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1) numerical circuit analysis, 2) Verilog, 3) electronic devices, 4) logic design, 5) digital IC design and layout experience, 6) analog IC design, 7) SPICE, and 8) computer... more |
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| Jul 26 | Senior DFT Engineer - Design For Te... | Cybercoders | Cupertino, CA |
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Engineer - Design For Test - Logic Design - Verilog RTL This position of Sr. DFT ... - Strong experience in Logic Design, Verilog RTL, Verification, and Static Timing... more |
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| Jul 26 | SOC/ASIC Verification Engineer | Milpitas, CA | |
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in developing system level test cases in verilog and C with PSL assertions Experience ... in developing system level test cases in verilog and C with PSL assertions Total exp... more |
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| Jul 26 | Firmware Engineer- Python, Perl, C | Tilera | San Jose, CA |
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equipment and procedures Familiarity with Verilog simulation environments Location and Travel This position is located in Westborough MA. A small amount of travel may be necessary... more |
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| Jul 26 | Microcontroller Programmer/FPGA HW Engineer | MICE Groups | Redwood City, CA |
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solutions on Xilinx FPGA using VHDL or Verilog Familiar with lab equipment such as DMM, Oscilloscope, Logic Analyzer, and Signal Generator Additionally Desired Skills: Excellent... more |
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| Jul 26 | Sr. Verification Engineer | Xilikon | San Jose, CA |
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& ATTRIBUTES:Implementing and maintaining Verilog/C/C++ test-benches and verification ... of Verilog & digital design is a mustSystem Verilog and DPI experience desirableThe... more |
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| Jul 26 | Engineer, Senior ASIC Design Verification | Marvell | Santa Clara, CA |
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design flow and design verification. Verilog RTL coding. Simulation test bench development/verification. Logic synthesis and static timing analysis. Lab Experience bringing up... more |
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| Jul 26 | Engineer, Sr Staff - IC Design | Broadcom | San Jose, CA |
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experience is a plus - Familiar with Verilog/System Verilog - Must be highly motivated, and be able to work both independently and as a member of team. Country United States... more |
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| Jul 26 | Senior Hardware Engineer | Infinera | Sunnyvale, CA |
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design highly desirable. * Experience with verilog FPGA design and implementation desirable. * Basic understanding of programming languages such as C and VB highly desirable. *... more |
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| Jul 26 | Engineer, Sr Staff - IC Design | Broadcom | Sunnyvale, CA |
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* VHDL/Verilog, C/C++ and Perl programming skills and also various simulation tools ... System verilog is a plus * Candidate must be a self-starter and must be able to work... more |
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| Jul 26 | FPGA Engineer | Oneten Technologies | Fremont, CA |
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Experienced with FPGA design using VHDL or Verilog andexperiences with some or all related EDA tools * Flexible, results-oriented problem-solver who requires minimal supervision *... more |
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| Jul 26 | Design Engineer | Kawasaki Microelectronics America | San Jose, CA |
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design and development including coding in Verilog/VHDL & simulation; perform digital ... with: high-speed digital VLSI design; RTL verilog, low power design and ability to... more |
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| Jul 26 | Engineer, Staff I - IC Design Verification | Broadcom | Sunnyvale, CA |
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coverage, HW/SW co-simulation; Verilog, Verilog PLI, VMM & SV assertions. - Proficient in Verilog/VHDL RTL design/simulation. - Working knowledge of C/C++, matlab, perl, tcl or... more |
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| Jul 26 | Engineer, Staff II - IC Design Verification | Broadcom | Sunnyvale, CA |
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coverage, HW/SW co-simulation; Verilog, Verilog PLI, VMM & SV assertions. - Proficient in Verilog/VHDL RTL design/simulation. - Working knowledge of C/C++, matlab, perl, tcl or... more |
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| Jul 26 | Engineer, Sr Staff - IC Design Verification | Broadcom | Sunnyvale, CA |
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coverage, HW/SW co-simulation; Verilog, Verilog PLI, VMM & SV assertions. - Proficient in Verilog/VHDL RTL design/simulation. - Working knowledge of C/C++, matlab, perl, tcl or... more |
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| Jul 26 | Engineer, Sr Staff - IC Design | Broadcom | Sunnyvale, CA |
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and cryptography preferred. Languages: Verilog, TCL, C required. Country United States State/Province California City/Town Sunnyvale Shift 1st Shift - Day Percent of Travel... more |
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| Jul 26 | Engineer, Principal - IC Design | Broadcom | San Jose, CA |
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traffic management (TM) functions. Using Verilog HDL language to implement hardware, ... experience is a plus - Familiar with Verilog/System Verilog - Must be highly... more |
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| Jul 26 | Intern | Broadcom | Sunnyvale, CA |
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- Familiar with VHDL/Verilog and Perl programming a big plus. - Some experience with various lab equipment (oscilloscope and logic analyzer, etc.) is even better. Country United... more |
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| Jul 26 | Intern | Broadcom | San Jose, CA |
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Excellent communication skills Knowledge of Verilog or VHDL design languages is a must Experience in digital logic design and verification is a must FPGA synthesis experience is a... more |
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| Jul 26 | Senior Principal Engineer/Director, Mixed-Signal ASIC Design | Infinera | Sunnyvale, CA |
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Cadence Spectre-RF, Mentor Calibre, Verilog-A, Virtuoso AMS, Skill language, Agilent ADS) is a must. 6. IC Technologies: High-speed IC technologies, including SiGe and CMOS. 7. IC... more |
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| Jul 26 | DFT LOGIC DESIGN LEAD | NVIDIA | Santa Clara, CA |
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- The candidate should be familiar with ASIC/Logic design flow including verilog coding, verification, RTL/full chip simulation, timing closure, and ECO. - General user support... more |
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| Jul 26 | Senior Verification Engineer | Broadcom | San Jose, CA |
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implementing testplans, developing System Verilog tests and checkers, creating ... experience is a plus - Familiar with System Verilog Country United States State/Province... more |
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| Jul 26 | ENGINEER.II.ASIC DEVELOPER ENGINEER | Cisco Systems | San Jose, CA |
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tools, scripting and programming languages (verilog, SV, C++, Perl, etc.). - Good problem solving skills. - Good communication skills and a team player. - Networking knowledge... more |
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| Jul 26 | Engineer, Principal - IC Design | Broadcom | San Jose, CA |
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using tcl, itcl, perl, C/C++ and system verilog programming languages to verify ... process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby,... more |
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| Jul 26 | Engineer, Sr Staff - IC Design | Broadcom | San Jose, CA |
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using tcl, itcl, perl, C/C++ and system verilog programming languages to verify ... process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby,... more |
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| Jul 26 | Intern | Broadcom | Sunnyvale, CA |
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* Understanding of hardware design principles and some HDL (VHDL/Verilog) literacy. * DSP experience is desirable. * RF experience is desirable. * Must have excellent written and... more |
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| Jul 26 | Silicon Validation Engineer | Broadcom | San Jose, CA |
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by reading acrhitecture documents and Verilog. - Develop best-in-class test plans for ASIC features. - Develop and debug best-in-class automated tests. - Develop new methodologies... more |
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| Jul 26 | Engineer, Sr Principal - Systems Design | Broadcom | Sunnyvale, CA |
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* Understanding of hardware design principles and some HDL (VHDL/Verilog) literacy. * DSP experience is desirable. * RF experience is desirable. * Must have excellent written and... more |
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| Jul 26 | Engineer , Staff I - Systems Design | Broadcom | Sunnyvale, CA |
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* Understanding of hardware design principles and some HDL (VHDL/Verilog) literacy. * DSP experience is desirable. * RF experience is desirable. * Must have excellent written and... more |
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| Jul 26 | Engineer, Principal - Systems Design | Broadcom | Sunnyvale, CA |
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* Understanding of hardware design principles and some HDL (VHDL/Verilog) literacy. * DSP experience is desirable. * RF experience is desirable. * Must have excellent written and... more |
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| Jul 26 | Senior Signal Integrity Engineer | Xilikon | San Jose, CA |
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desiredKnowledge of tools such as HSPICE or Verilog-A/AMS , Matlab or Perl scripts, CST MWS or HFSS 3D field solver Knowledge of Allegro PCB tool EXPERIENCE & EDUCATION:BS/CS... more |
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| Jul 26 | Sr. VLSI Design Engineer - Video | Oneten Technologies | Sunnyvale, CA |
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functions. Programming: Proficient in Verilog, C, Unix shell scripting, Design Compiler Labs: Demonstrable experience in using logic analyzer, oscilloscope Problem solving:... more |
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| Jul 26 | VLSI Design Engineer - Video | Zoran | Sunnyvale, CA |
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functions. * Programming:Proficient in Verilog, C, Unix shell scripting, Design Compiler * Labs: Demonstrable experience in using logic analyzer, oscilloscope * Problem... more |
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| Jul 26 | Engineer, Sr Staff - IC Design | Broadcom | Santa Clara, CA |
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to the ASIC development process including Verilog, VHDL, Unix Scripting, and C. Working experience needs to demonstrate the technical expertise in successful completion of... more |
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| Jul 26 | Engineer, Staff II - IC Design | Broadcom | Sunnyvale, CA |
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- Proficient in Verilog/VHDL RTL design/simulation. - Knowledge of chip design methodology. - Working knowledge of C/C++, matlab, perl, tcl or other scripting language is a plus. more |
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| Jul 26 | Engineer, Sr Staff - IC Design | Broadcom | Sunnyvale, CA |
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- Proficient in Verilog/VHDL RTL design/simulation. - Knowledge of chip design methodology. - Working knowledge of C/C++, matlab, perl, tcl or other scripting language is a plus. more |
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| Jul 26 | Engineer, Principal - IC Design | Broadcom | Sunnyvale, CA |
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Highly skilled in Verilog/VHDL RTL design/simulation/verification. Knowledge of chip design methodology, and experience with logic synthesis and timing closure. Knowledge of... more |
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| Jul 26 | Verifications Engineer | Xilikon | San Jose, CA |
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test development RTL Design Understanding (Verilog preferred)PreferredMS in EE, Computer Engineering, or equivalent field.Experience with embedded firmware / low level drivers /... more |
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| Jul 26 | Engineer, Sr Staff - Product Applications | Broadcom | Sunnyvale, CA |
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with Verilog HDL -- can read and understand Verilog - Experience with low-level (firmware, device driver) software -- can read and understand C/C++ code, must be able to write... more |
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| Jul 25 | Digital, ASIC Design Engineer | Chip Source | Fremont, CA |
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icro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate in design of communications SoCs. Verilog design and verification... more |
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| Jul 25 | Digital, ASIC Design Engineer | Chip Source | San Jose, CA |
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icro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate in design of communications SoCs. Verilog design and verification... more |
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| Jul 25 | CAD Engineer - Synthesis | R & R Staffing | San Jose, CA |
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new methodologies to support Language VHDL/Verilog Synthesis and Simulation.REQUIRED ... Timing Analysis essential.Knowledge of VHDL/Verilog desired. Good Understanding of Key... more |
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| Jul 25 | Sr. ASIC Design Verification Engineer | R & R Staffing | Milpitas, CA |
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Verification experience.Knowledge of Verilog and C required.Prior experience in networking (Ethernet, ATM: UTOPIA, AAL5, AAL2, AAL1) or Telecommunication ASICs is... more |
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| Jul 25 | Digital Design Engineer - ASIC Design - IC Designer - RTL - CIS | Cybercoders | Palo Alto, CA |
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asic, cmos, cis, imaging, image sensors, Verilog, image processing, graphics, ... sensors- Experience with RTL coding in Verilog, verification, validation,... more |
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| Jul 25 | Engineering Intern | Intel | Santa Clara, CA |
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Perl - RTL design using Verilog or System Verilog, RTL simulation and analysis tools, synthesis, and timing analysis/convergence - actual design experience in an industrial design... more |
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| Jul 25 | Pre-Si Validation Engineer | Intel | Santa Clara, CA |
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of uArchitecture, proficiency in System Verilog, VCS, Specman and scripting - Experience in validation test environment, test automation, test content, coverage and enabling... more |
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| Jul 25 | Pre-Si Validation Engineer | Intel | Santa Clara, CA |
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of uArchitecture, proficiency in System Verilog, VCS, Specman and scripting - Experience in validation test environment, test automation, test content, coverage and enabling... more |
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| Jul 25 | Pre-Si Validation Engineer | Intel | Santa Clara, CA |
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of uArchitecture, proficiency in System Verilog, VCS, Specman and scripting - Experience in validation test environment, test automation, test content, coverage and enabling... more |
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| Jul 25 | HAH - Aerospace and Defense Co-op | Xilinx | San Jose, CA |
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and FPGA design.Simulation (MTI, VCS, NC-Verilog) and verification techniquesHands-on experience with lab equipment including logic analyzers and oscilloscopes. Good written and... more |
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| Jul 25 | Mixed Signal Sim DA Architect | Intel | Santa Clara, CA |
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tool and flow levels ?SPICE simulation, Verilog-A/AMS coding & simulation - Minimum 15 years experience in scripting and/or programming expertise with SKILL, TCL, Perl, UNIX... more |
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| Jul 24 | DV Consultant | Advanced Resources | San Jose, CA |
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Most of the work is at the block/cluster level and the tools are System Verilog with VVM ... Design Verification Environment in System Verilog and who can write well structured... more |
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| Jul 24 | SOC/ASIC Verification Engineer | Milpitas, CA | |
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in developing system level test cases in verilog and C, with PSL assertions - Experience with and thorough understanding of SOC simulation and verification methodology, tools, and... more |
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| Jul 24 | ASIC Design Engineer | SanDisk | Milpitas, CA |
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and verification; Synthesis; Xilinx; Verilog, and C.SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401... more |
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| Jul 24 | Design Engineer | SanDisk | Milpitas, CA |
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4) MOS VLSI circuit design, 5) SPICE/Verilog simulator, 6) static memory, 7) logic design. SanDisk offers a highly competitive compensation package and great benefits, which... more |
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| Jul 24 | SOC/ASIC Verification Engineer | Aesinc | Milpitas, CA |
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in developing system level test cases in verilog and C, with PSL assertions- Experience with and thorough understanding of SOC simulation and verification methodology, tools, and... more |
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