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Jul 29 Component Design Engineer Intel Folsom, CA

methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Mod, elsim simulators - Knowledge of PC Architecture Preferred Requirements: -... more

Jul 29 Graduate Intern Technical Intel Folsom, CA

activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more

Jul 29 Pre-Si Design Automation Engineer Intel Folsom, CA

for RTL Verification including verilog simulation with VCS, SystemVerilog Testbench/OVM, and/or expertise with Formal Property Verification. - 8+ years experience with RTL... more

Jul 29 Design Automation Engineer Intel Folsom, CA

- 1-3 years experience with RTL (HDL, Verilog*, and others) formats. Must also be familiar with the Synthesis* flow concepts. Additional qualifications include: - 1-3 years... more

Jul 27 Component Design Engineer Intel Folsom, CA

methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Mod, elsim simulators - Knowledge of PC Architecture Preferred Requirements: -... more

Jul 27 Design Automation Engineer Intel Folsom, CA

- 1-3 years experience with RTL (HDL, Verilog*, and others) formats. Must also be familiar with the Synthesis* flow concepts. Additional qualifications include: - 1-3 years... more

Jul 26 Graduate Intern Technical Intel Folsom, CA

activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more

Jul 25 Digital, ASIC Design Engineer Chip Source Sacramento, CA

icro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate in design of communications SoCs. Verilog design and verification... more

Jul 20 Emulation Engineer Abacus Service Sacramento, CA

at gate level - Experience coding VHDL and Verilog RTL within the UNIX environment - Experience and strong debugging hardware at the board and system level - Strong understanding... more

Jul 15 Presilicon Validation Engineer Intel Folsom, CA

methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more

Jul 15 Presilicon Validation Engineer Intel Folsom, CA

methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more

Jul 15 Validation Engineer Intel Folsom, CA

[Very High-level Design Language (VHDL), Verilog* or Intel's Hardware Description Language (iHDL)] would be an added advantage - Validation and familiarity of industry standard... more

Jul 08 Component Design Engineer Intel Folsom, CA

involve logic design using System Verilog, functional logic verification, ... knowledge - Good knowledge of UNIX* tools, Verilog*, Tcl and Perl scripting - Excellent... more

Jul 08 Component Design Engineer Intel Folsom, CA

design and validation, Synopsys* synthesis, Verilog* gate level simulation, performance ... Design Compiler, Synopsys* Primetime, Verilog* RTL language, Perl scripting, C/C++... more

Jul 08 Component Design Engineer Intel Folsom, CA

(monitors, BFMs and others) in System Verilog*. You will act as a consultant to ... - Ability to develop RTL Models in Verilog - Ability to plan and execute block... more

Jul 08 Graduate Intern Technical Intel Folsom, CA

activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more

Jul 08 emulation engineer Intel Folsom, CA

- proficient in C/C++, Verilog, Linux-based development environments and tools, scripting ... emulation technology, HDL modeling (Verilog*), simulation model debug, and... more

Jul 08 Graduate Intern Technical Intel Folsom, CA

activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more

Jul 08 Intern component design engg Intel Folsom, CA

Design Compiler, Synopsys* Primetime*, Verilog* Register Transfer Level (RTL) language and Perl scripting Job Category : Engineering Primary Location : USA-California,... more

Jul 08 Validation Intern Intel Folsom, CA

with High-level Design Language (VHDL) or Verilog* simulation Job Category : Engineering Primary Location : USA-California, Folsom Full/Part Time : Full Time Job Type :... more

Jul 08 Logic Verification Engineer Intel Folsom, CA

of logic design concepts - Expertise in Verilog*, SystemVerilog*, AVM*/OVM*, Perl scripting, and VCS* simulator - Expertise in functional coverage concepts/implementation - Strong... more

Jul 08 Logic Verification Engineer Intel Folsom, CA

of logic design concepts - Expertise in Verilog*, SystemVerilog*, AVM*/OVM*, Perl scripting, and VCS* simulator - Expertise in functional coverage concepts/implementation - Strong... more

Jul 08 Logic Verification Engineer Intel Folsom, CA

and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more

Jul 08 Pre-Si Validation Tech Lead Intel Folsom, CA

tools and methodologies including: System Verilog, Java, Perl, object oriented constructs, VCS/synopsis simulators 7+ years experience CPU verification and/or design 5 + years... more

Jul 08 Logic Verification Engineer Intel Folsom, CA

and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more

Jul 08 Component Design Engineer Intel Folsom, CA

circuit simulation tools such as SPICE, Verilog, etc. The following qualifications would be an added advantage: - Familiarity with CMOS transistor and semiconductor device layout... more

Jul 08 Sr Design Automation Engineer Intel Folsom, CA

design and hardware modeling in system verilog. 5+ years experience in debug and problem solving skills at the tool and flow levels 5+ years experience scripting and/or... more

Jul 08 Hardware Engineer Intel Sacramento, CA

one of the following areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object... more

Jul 08 Component Design Engineer Intel Sacramento, CA

the following techniques/tools: - System Verilog - Synopsys VCS Simulator - OVM methodology - Assertion based coverage measurement Protocol experience with complex serial PHYs... more

Jul 08 Sr. Component Design Engineer Intel Folsom, CA

synthesis, and timing analysis -System Verilog knowledge is a plus 7 years experience debugging skills at all stages of chip development Preferred Requirements: Experience working... more

Jul 08 Sr. Component Design Engineer Intel Folsom, CA

synthesis, and timing analysis (System Verilog knowledge is a plus) - Good debugging skills at all stages of chip development is an added advantage - Experience working with... more

Jul 08 Sr. Component Design Engineer Intel Folsom, CA

development Preferred Requirements: System Verilog knowledge is a plus Experience working with cross-functional and cross-site teams; leadership experience would be an added... more

Jul 08 Mixed Signal Sim DA Architect Intel Folsom, CA

tool and flow levels ?SPICE simulation, Verilog-A/AMS coding & simulation - Minimum 15 years experience in scripting and/or programming expertise with SKILL, TCL, Perl, UNIX... more

Jul 08 Component Design Engineer Intel Sacramento, CA

components (monitors, BFMs etc.) in System Verilog, BMODs, interfacing with Structural Design and Analog/Circuit Design teams. Qualifications You should possess a relevant... more

Jun 29 VLSI Design Senior Developer with Verilog experience Sacramento, CA

Verilog experience is required Engage Circuit Designers to debug logic mismatches Requirement collection, problem formulation, solution proposal, implementation, testing,... more

Jun 29 Sr. FPGA Firmware Engineer - ASIC design experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 28 Verilog Senior Design Engineer with Xilinx experience Sacramento, CA

Write scripts to automate some tasks of the Verilog design/verification process Select components and equipment based on analysis of specifications and reliability Develops and... more

Jun 28 FPGA Senior Designer - VHDL programming experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 27 Senior VLSI Circuit Design Engineer with Verilog experience Sacramento, CA

Verilog experience is required Engage Circuit Designers to debug logic mismatches Requirement collection, problem formulation, solution proposal, implementation, testing,... more

Jun 27 Senior Hardware FPGA Engineer - R&D experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 26 FPGA Electronic Engineer - JHDL programming experience Sacramento, CA

Min 3+ years of experience Technical Skills Verilog FPGA Design experience Experience with MATLB toolkit Education BS or equivalent Degree in Engineering Additional Skills Highly... more

Jun 25 Senior Verilog Design Engineer with MATLAB experience Sacramento, CA

Write scripts to automate some tasks of the Verilog design/verification process Select components and equipment based on analysis of specifications and reliability Develops and... more

Jun 25 ASIC Designer Cornerstone Staffing Solutions Roseville, CA

in Digital Design with at least 5+ years in Verilog / Synthesis-based ASIC Design * ... power management PMICS is highly desired * Verilog language and simulation verification... more

Jun 25 Sr FPGA Design Engineer - DSP experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 24 Sr Verilog Engineer -Ethernet Experience Sacramento, CA

Write scripts to automate some tasks of the Verilog design/verification process Select components and equipment based on analysis of specifications and reliability Develops and... more

Jun 24 Sr FPGA Development Engineer with Xilinx FPGA experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 23 FPGA Senior Developer - Network protocol experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 22 Development Engineer - Entry Level IBM Sacramento, CA

and programming (for example, C, VHDL, Verilog), design, test, and communication skills. Team-based experience in DSP, circuit/logic design, power systems, verification, analysis... more

Jun 22 Senior Hardware FPGA Engineer - ASIC design experience Sacramento, CA

Minimum 5+ years Technical Skills Verilog FPGA Design experience Experience with MATLB toolkit Education BS or equivalent Degree in Engineering Additional Skills Highly motivated... more

Jun 21 FPGA Senior Engineer - Research & Development Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 20 Sr FPGA Design & Validation Engineer COMSEC design experience Sacramento, CA

hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more

Jun 14 Sr. Component Design Engineer Intel Folsom, CA

development Preferred Requirements: System Verilog knowledge is a plus Experience working with cross-functional and cross-site teams; leadership experience would be an added... more

Jun 02 Logic Verification Engineer Intel Folsom, CA

and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more

Jun 02 Component Design Engineer Intel Folsom, CA

knowledge - Good knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the... more

Jun 01 Presilicon Validation Engineer Intel Folsom, CA

methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more

Jun 01 Presilicon Validation Engineer Intel Folsom, CA

methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more

May 26 Design Engineering Manager Intel Folsom, CA

perience driving operational improvement and excellence - Strong technical knowledge of logic design and validation, experience in System Verilog a plus - Knowledge of CPU and... more

May 25 Sr. Component Design Engineer Intel Folsom, CA

synthesis, and timing analysis -System Verilog knowledge is a plus 7 years experience debugging skills at all stages of chip development Preferred Requirements: Experience working... more

May 24 Sr Design Automation Engineer Intel Folsom, CA

design and hardware modeling in system verilog. 5 years experience in debug and problem solving skills at the tool and flow levels 5 years experience scripting and/or programming... more

May 19 Sr. Component Design Engineer Intel Folsom, CA

synthesis, and timing analysis (System Verilog knowledge is a plus) - Good debugging skills at all stages of chip development is an added advantage - Experience working with... more

May 17 Pre-Si Validation Tech Lead Intel Folsom, CA

tools and methodologies including: System Verilog, Java, Perl, object oriented constructs, VCS/synopsis simulators 7 years experience CPU verification and/or design 5 years... more

Apr 27 Logic Verification Engineer Intel Folsom, CA

and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more

Apr 22 Component Design Engineer Intel Folsom, CA

circuit simulation tools such as SPICE, Verilog, etc. The following qualifications would be an added advantage: - Familiarity with CMOS transistor and semiconductor device layout... more

Apr 21 Component Design Engineer Intel Folsom, CA

(monitors, BFMs and others) in System Verilog*. You will act as a consultant to ... of advanced RTL design methodologies using VCS, System Verilog and OVM is a... more

Mar 17 Component Design Engineer Intel Folsom, CA

involve logic design using System Verilog, functional logic verification, ... knowledge - Good knowledge of UNIX* tools, Verilog*, Tcl and Perl scripting - Excellent... more

Feb 18 Component Design Engineer Intel Folsom, CA

design and validation, Synopsys* synthesis, Verilog* gate level simulation, performance ... Synopsys* Design Compiler, Synopsys* Primetime, Verilog* RTL language, Perl scripting,... more

Feb 18 Intern component design engg Intel Folsom, CA

plication Specific Integrated Circuit (ASIC) design tools such as Modelsim* logic simulator, Synopsys* Design Compiler, Synopsys* Primetime*, Verilog* Register Transfer Level... more

Feb 17 Logic Verification Engineer Intel Folsom, CA

of logic design concepts - Expertise in Verilog*, SystemVerilog*, AVM*/OVM*, Perl scripting, and VCS* simulator - Expertise in functional coverage concepts/implementation - Strong... more

Feb 09 emulation engineer Intel Folsom, CA

- proficient in C/C , Verilog, Linux-based development environments and tools, scripting ... emulation technology, HDL modeling (Verilog*), simulation model debug, and... more