Verilog jobs - Folsom, CA
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| Jul 29 | Component Design Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Mod, elsim simulators - Knowledge of PC Architecture Preferred Requirements: -... more |
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| Jul 29 | Graduate Intern Technical | Intel | Folsom, CA |
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activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more |
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| Jul 29 | Pre-Si Design Automation Engineer | Intel | Folsom, CA |
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for RTL Verification including verilog simulation with VCS, SystemVerilog Testbench/OVM, and/or expertise with Formal Property Verification. - 8+ years experience with RTL... more |
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| Jul 29 | Design Automation Engineer | Intel | Folsom, CA |
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- 1-3 years experience with RTL (HDL, Verilog*, and others) formats. Must also be familiar with the Synthesis* flow concepts. Additional qualifications include: - 1-3 years... more |
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| Jul 27 | Component Design Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Mod, elsim simulators - Knowledge of PC Architecture Preferred Requirements: -... more |
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| Jul 27 | Design Automation Engineer | Intel | Folsom, CA |
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- 1-3 years experience with RTL (HDL, Verilog*, and others) formats. Must also be familiar with the Synthesis* flow concepts. Additional qualifications include: - 1-3 years... more |
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| Jul 26 | Graduate Intern Technical | Intel | Folsom, CA |
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activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more |
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| Jul 25 | Digital, ASIC Design Engineer | Chip Source | Sacramento, CA |
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icro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate in design of communications SoCs. Verilog design and verification... more |
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| Jul 20 | Emulation Engineer | Abacus Service | Sacramento, CA |
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at gate level - Experience coding VHDL and Verilog RTL within the UNIX environment - Experience and strong debugging hardware at the board and system level - Strong understanding... more |
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| Jul 15 | Presilicon Validation Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more |
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| Jul 15 | Presilicon Validation Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more |
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| Jul 15 | Validation Engineer | Intel | Folsom, CA |
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[Very High-level Design Language (VHDL), Verilog* or Intel's Hardware Description Language (iHDL)] would be an added advantage - Validation and familiarity of industry standard... more |
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| Jul 08 | Component Design Engineer | Intel | Folsom, CA |
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involve logic design using System Verilog, functional logic verification, ... knowledge - Good knowledge of UNIX* tools, Verilog*, Tcl and Perl scripting - Excellent... more |
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| Jul 08 | Component Design Engineer | Intel | Folsom, CA |
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design and validation, Synopsys* synthesis, Verilog* gate level simulation, performance ... Design Compiler, Synopsys* Primetime, Verilog* RTL language, Perl scripting, C/C++... more |
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| Jul 08 | Component Design Engineer | Intel | Folsom, CA |
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(monitors, BFMs and others) in System Verilog*. You will act as a consultant to ... - Ability to develop RTL Models in Verilog - Ability to plan and execute block... more |
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| Jul 08 | Graduate Intern Technical | Intel | Folsom, CA |
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activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more |
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| Jul 08 | emulation engineer | Intel | Folsom, CA |
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- proficient in C/C++, Verilog, Linux-based development environments and tools, scripting ... emulation technology, HDL modeling (Verilog*), simulation model debug, and... more |
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| Jul 08 | Graduate Intern Technical | Intel | Folsom, CA |
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activities - - logic design using System Verilog - functional logic verification ... Very High Level Design Language (VHDL) or Verilog* - Familiarity with Very High System... more |
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| Jul 08 | Intern component design engg | Intel | Folsom, CA |
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Design Compiler, Synopsys* Primetime*, Verilog* Register Transfer Level (RTL) language and Perl scripting Job Category : Engineering Primary Location : USA-California,... more |
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| Jul 08 | Validation Intern | Intel | Folsom, CA |
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with High-level Design Language (VHDL) or Verilog* simulation Job Category : Engineering Primary Location : USA-California, Folsom Full/Part Time : Full Time Job Type :... more |
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| Jul 08 | Logic Verification Engineer | Intel | Folsom, CA |
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of logic design concepts - Expertise in Verilog*, SystemVerilog*, AVM*/OVM*, Perl scripting, and VCS* simulator - Expertise in functional coverage concepts/implementation - Strong... more |
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| Jul 08 | Logic Verification Engineer | Intel | Folsom, CA |
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of logic design concepts - Expertise in Verilog*, SystemVerilog*, AVM*/OVM*, Perl scripting, and VCS* simulator - Expertise in functional coverage concepts/implementation - Strong... more |
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| Jul 08 | Logic Verification Engineer | Intel | Folsom, CA |
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and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more |
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| Jul 08 | Pre-Si Validation Tech Lead | Intel | Folsom, CA |
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tools and methodologies including: System Verilog, Java, Perl, object oriented constructs, VCS/synopsis simulators 7+ years experience CPU verification and/or design 5 + years... more |
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| Jul 08 | Logic Verification Engineer | Intel | Folsom, CA |
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and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more |
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| Jul 08 | Component Design Engineer | Intel | Folsom, CA |
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circuit simulation tools such as SPICE, Verilog, etc. The following qualifications would be an added advantage: - Familiarity with CMOS transistor and semiconductor device layout... more |
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| Jul 08 | Sr Design Automation Engineer | Intel | Folsom, CA |
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design and hardware modeling in system verilog. 5+ years experience in debug and problem solving skills at the tool and flow levels 5+ years experience scripting and/or... more |
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| Jul 08 | Hardware Engineer | Intel | Sacramento, CA |
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one of the following areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object... more |
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| Jul 08 | Component Design Engineer | Intel | Sacramento, CA |
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the following techniques/tools: - System Verilog - Synopsys VCS Simulator - OVM methodology - Assertion based coverage measurement Protocol experience with complex serial PHYs... more |
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| Jul 08 | Sr. Component Design Engineer | Intel | Folsom, CA |
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synthesis, and timing analysis -System Verilog knowledge is a plus 7 years experience debugging skills at all stages of chip development Preferred Requirements: Experience working... more |
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| Jul 08 | Sr. Component Design Engineer | Intel | Folsom, CA |
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synthesis, and timing analysis (System Verilog knowledge is a plus) - Good debugging skills at all stages of chip development is an added advantage - Experience working with... more |
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| Jul 08 | Sr. Component Design Engineer | Intel | Folsom, CA |
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development Preferred Requirements: System Verilog knowledge is a plus Experience working with cross-functional and cross-site teams; leadership experience would be an added... more |
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| Jul 08 | Mixed Signal Sim DA Architect | Intel | Folsom, CA |
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tool and flow levels ?SPICE simulation, Verilog-A/AMS coding & simulation - Minimum 15 years experience in scripting and/or programming expertise with SKILL, TCL, Perl, UNIX... more |
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| Jul 08 | Component Design Engineer | Intel | Sacramento, CA |
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components (monitors, BFMs etc.) in System Verilog, BMODs, interfacing with Structural Design and Analog/Circuit Design teams. Qualifications You should possess a relevant... more |
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| Jun 29 | VLSI Design Senior Developer with Verilog experience | Sacramento, CA | |
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Verilog experience is required Engage Circuit Designers to debug logic mismatches Requirement collection, problem formulation, solution proposal, implementation, testing,... more |
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| Jun 29 | Sr. FPGA Firmware Engineer - ASIC design experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 28 | Verilog Senior Design Engineer with Xilinx experience | Sacramento, CA | |
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Write scripts to automate some tasks of the Verilog design/verification process Select components and equipment based on analysis of specifications and reliability Develops and... more |
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| Jun 28 | FPGA Senior Designer - VHDL programming experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 27 | Senior VLSI Circuit Design Engineer with Verilog experience | Sacramento, CA | |
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Verilog experience is required Engage Circuit Designers to debug logic mismatches Requirement collection, problem formulation, solution proposal, implementation, testing,... more |
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| Jun 27 | Senior Hardware FPGA Engineer - R&D experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 26 | FPGA Electronic Engineer - JHDL programming experience | Sacramento, CA | |
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Min 3+ years of experience Technical Skills Verilog FPGA Design experience Experience with MATLB toolkit Education BS or equivalent Degree in Engineering Additional Skills Highly... more |
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| Jun 25 | Senior Verilog Design Engineer with MATLAB experience | Sacramento, CA | |
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Write scripts to automate some tasks of the Verilog design/verification process Select components and equipment based on analysis of specifications and reliability Develops and... more |
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| Jun 25 | ASIC Designer | Cornerstone Staffing Solutions | Roseville, CA |
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in Digital Design with at least 5+ years in Verilog / Synthesis-based ASIC Design * ... power management PMICS is highly desired * Verilog language and simulation verification... more |
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| Jun 25 | Sr FPGA Design Engineer - DSP experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 24 | Sr Verilog Engineer -Ethernet Experience | Sacramento, CA | |
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Write scripts to automate some tasks of the Verilog design/verification process Select components and equipment based on analysis of specifications and reliability Develops and... more |
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| Jun 24 | Sr FPGA Development Engineer with Xilinx FPGA experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 23 | FPGA Senior Developer - Network protocol experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 22 | Development Engineer - Entry Level | IBM | Sacramento, CA |
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and programming (for example, C, VHDL, Verilog), design, test, and communication skills. Team-based experience in DSP, circuit/logic design, power systems, verification, analysis... more |
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| Jun 22 | Senior Hardware FPGA Engineer - ASIC design experience | Sacramento, CA | |
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Minimum 5+ years Technical Skills Verilog FPGA Design experience Experience with MATLB toolkit Education BS or equivalent Degree in Engineering Additional Skills Highly motivated... more |
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| Jun 21 | FPGA Senior Engineer - Research & Development | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 20 | Sr FPGA Design & Validation Engineer COMSEC design experience | Sacramento, CA | |
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hardware experience required Verilog FPGA Design experience Education Master's Degree Additional Skills Highly motivated to learn new and existing technologies Ability to support... more |
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| Jun 14 | Sr. Component Design Engineer | Intel | Folsom, CA |
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development Preferred Requirements: System Verilog knowledge is a plus Experience working with cross-functional and cross-site teams; leadership experience would be an added... more |
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| Jun 02 | Logic Verification Engineer | Intel | Folsom, CA |
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and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more |
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| Jun 02 | Component Design Engineer | Intel | Folsom, CA |
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knowledge - Good knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the... more |
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| Jun 01 | Presilicon Validation Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more |
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| Jun 01 | Presilicon Validation Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C Preferred Requirements: Knowledge of PC Architecture is... more |
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| May 26 | Design Engineering Manager | Intel | Folsom, CA |
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perience driving operational improvement and excellence - Strong technical knowledge of logic design and validation, experience in System Verilog a plus - Knowledge of CPU and... more |
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| May 25 | Sr. Component Design Engineer | Intel | Folsom, CA |
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synthesis, and timing analysis -System Verilog knowledge is a plus 7 years experience debugging skills at all stages of chip development Preferred Requirements: Experience working... more |
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| May 24 | Sr Design Automation Engineer | Intel | Folsom, CA |
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design and hardware modeling in system verilog. 5 years experience in debug and problem solving skills at the tool and flow levels 5 years experience scripting and/or programming... more |
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| May 19 | Sr. Component Design Engineer | Intel | Folsom, CA |
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synthesis, and timing analysis (System Verilog knowledge is a plus) - Good debugging skills at all stages of chip development is an added advantage - Experience working with... more |
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| May 17 | Pre-Si Validation Tech Lead | Intel | Folsom, CA |
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tools and methodologies including: System Verilog, Java, Perl, object oriented constructs, VCS/synopsis simulators 7 years experience CPU verification and/or design 5 years... more |
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| Apr 27 | Logic Verification Engineer | Intel | Folsom, CA |
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and ASIC design flow - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more |
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| Apr 22 | Component Design Engineer | Intel | Folsom, CA |
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circuit simulation tools such as SPICE, Verilog, etc. The following qualifications would be an added advantage: - Familiarity with CMOS transistor and semiconductor device layout... more |
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| Apr 21 | Component Design Engineer | Intel | Folsom, CA |
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(monitors, BFMs and others) in System Verilog*. You will act as a consultant to ... of advanced RTL design methodologies using VCS, System Verilog and OVM is a... more |
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| Mar 17 | Component Design Engineer | Intel | Folsom, CA |
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involve logic design using System Verilog, functional logic verification, ... knowledge - Good knowledge of UNIX* tools, Verilog*, Tcl and Perl scripting - Excellent... more |
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| Feb 18 | Component Design Engineer | Intel | Folsom, CA |
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design and validation, Synopsys* synthesis, Verilog* gate level simulation, performance ... Synopsys* Design Compiler, Synopsys* Primetime, Verilog* RTL language, Perl scripting,... more |
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| Feb 18 | Intern component design engg | Intel | Folsom, CA |
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plication Specific Integrated Circuit (ASIC) design tools such as Modelsim* logic simulator, Synopsys* Design Compiler, Synopsys* Primetime*, Verilog* Register Transfer Level... more |
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| Feb 17 | Logic Verification Engineer | Intel | Folsom, CA |
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of logic design concepts - Expertise in Verilog*, SystemVerilog*, AVM*/OVM*, Perl scripting, and VCS* simulator - Expertise in functional coverage concepts/implementation - Strong... more |
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| Feb 09 | emulation engineer | Intel | Folsom, CA |
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- proficient in C/C , Verilog, Linux-based development environments and tools, scripting ... emulation technology, HDL modeling (Verilog*), simulation model debug, and... more |
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