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Sep 20 Speech Recognition - Computer Algorithms Automatic Speech Engineer Intouch Staffing Professionals Santa Clara, CA

or Python scripting experience Knowledge of SystemC US Citizens and all other parties authorized to work in the US are encouraged to apply. We are unable to sponsor H1B Visarsquos... more

Sep 20 Electronic System-Level (ESL) Modeler (SystemC, SoC) HCL America Hillsboro, OR

(as many) Hardware modelling using (SystemC, C++, DML, TLM Standards, HDL) OSCI, ... and verifiable professional experience. systemc c c++ esl tlm microprocessor... more

Sep 20 Computer Algorithms Automatic Speech recognition Intouch Staffing Professionals Sunnyvale, CA

scripting experience middot Knowledge of SystemC US Citizens and all other parties authorized to work in the US are encouraged to apply. We are unable to sponsor H1B Visarsquos at... more

Sep 19 Embedded HW/SW Design Engineer Job Leidos San Diego, CA

6+ years experience with Verilog, VHDL, SystemC, SystemVerilog, and/or Matlab for the deve ... •Platform exploration (SystemC/TLM) for custom SoC using industry standard tools... more

Sep 19 Senior Computer Architect / Computer Engineer Job Leidos San Diego, CA

8+ years of experience with Verilog, VHDL, SystemC, and/or SystemVerilog for the ... •Platform exploration (SystemC/TLM) for custom SoC using industry standard tools... more

Sep 19 Computer Architect / Computer Engineer Job Leidos San Diego, CA

4+ years of experience with Verilog, VHDL, SystemC, and/or SystemVerilog for the ... •Platform exploration (SystemC/TLM) for custom SoC using industry standard tools... more

Sep 17 Principal R&D Application Engineer San Jose, CA

programming and system simulation using SystemC is a plus Must have excellent written and verbal communication skills as well as good problem solving skills. Able to travel 2 to... more

Sep 16 Patient Care Assistant St. Luke's University Health Network Coaldale, PA

orders using order entry computer systemc) Maintains sufficient unit suppliesd) Maintains unit statistics, manuals and logs as assignede) Communicates between members of the... more

Sep 13 Incisive Simulator Product Expert Cadence Design Systems Austin, TX

experience using SystemVerilog/e/SystemC/Vera * Hands on Design experience using Verilog, VHDL. * Knowledge of Verification IP, and code & functional coverage technologies. *... more

Sep 13 FPGA/ASIC Engineer General Dynamics Arizona

C/C++, Perl, and UNIX. Proficiency with SystemC and a big plus. Knowledge of OVM, UVM or VMM is required. Knowledge of high-speed peripheral interfaces (PCI/SpaceWire, SERDES,... more

Sep 13 CPU Model Engineer ARM Austin, TX

microarchitecture * Prior knowledge of SystemC / TLM2 would be an advantage It is essential for the successful applicant to: * Demonstrate enthusiasm, drive and diligence * Work... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

include: Developing behavioral models in SystemC and C++ and methodology development for logic verification. RTL and Gate level simulation/verification. Support of assertions and... more

Sep 11 CPU Model Engineer Middlesex Community College Austin, TX

microarchitecture * Prior knowledge of SystemC / TLM2 would be an advantage It is essential for the successful applicant to: * Demonstrate enthusiasm, drive and diligence * Work... more

Sep 11 Design Verification and Methodology Deployment Engineer Encore Semi San Diego, CA

languages: C, C++, and SystemC. • Experience in functional verification EDA tools: VCS, IUS, ModelSim, Jasper, 0-in, IFV, OneSpin, SLEC, etc is highly desired. • Scripting and... more

Sep 11 Product Engineering SW Architect - Semi and System Software Wipro Portland, OR

Embedded SW, C++, SystemC/ TLM2/ Perl/ Python/ Basic Architecture concepts, SW processes?Basic ISA modeling / IP Modeling / Writing Tests / AutomationSOC Modeling ( Func / Cycle... more

Sep 11 Senior ASIC Verification Engineer Results Center Santa Clara, CA

Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments... more

Sep 11 Senior ASIC Verification Engineer Marvell Santa Clara, CA

Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments... more

Sep 11 Intern: ASIC Engineer Juniper Networks Sunnyvale, CA

or Computer Science * Strong Verilog, SystemC or C/C++, Perl/shell skills. * Must have good leadership and communication skills. * Networking experience is highly desirable, but... more

Sep 10 Manufacturing Engineer Altec Industries Daleville, VA

the implementation of the Altec Production SystemC. Improve manufacturing efficiency by identifying and eliminating waste, improving quality and supporting a safe work... more

Sep 08 Staff R&D Simulation Tools Engineer Synopsys Sunnyvale, CA

new features for the transaction level SystemC models as well as cycle accurate ... Experience with SystemC 2.x, OSCI SystemC, TLM 2.0 API standards a plus ·... more

Sep 08 Intern- SoC Performance Modeling Job Micron Boise, ID

models. Model development will be in SystemC and SystemVerilog. Canidate should be ... - C/C++, SystemC, or SystemVerilog, and Python experience is desired... more

Sep 08 Intern- Firmware/Microcode Job Micron Boise, ID

- Contributing to the architecture of SystemC models of the Advanced Memory Systems ... software development tools, debuggers, SystemC, and simulation techniques is a plus. more

Sep 06 Principal EDA Software Engineer- Formal Verification CAE Recruiters San Jose, CA

abstract specifications written in C++/SystemC and their corresponding RTL implementations and contributing to leading edge software development for this tool. This will involve... more

Sep 05 Intern – ASIC HW Engineer InterDigital King of Prussia, PA

methodology including RTL (VHDL, Verilog, SystemC), simulation, synthesis, etc. Job ... including RTL (VHDL, Verilog, SystemC), simulation, synthesis, etc. · Pragmatic... more

Sep 05 Verification Engineer Ee-recruiters Santa Clara, CA

desired Skills that are pluses: - C++ or SystemC programming What you'll be doing: - ... SystemVerilog, OVM / UVM / or VMM, C++ or SystemC, "verification... more

Sep 04 MTS ASIC/ Layout Design Engineer Amd | Seamicro Massachusetts

acceptable SV/VMM, SV, C++, SystemC, Vera, E) • Mastery of a scripting language (Shell, Perl, Python, Ruby) • Verification functional coverage using industry standard coverage... more

Sep 04 Sr Staff Design Verification Engineer Broadcom San Jose, CA

languages (Verilog/SystemVerilog/SystemC/VHDL), high level languages (C++), ... in languages such as Systemverilog, SystemC, C/C++, Perl, TCL/TK. * Strong... more

Sep 03 Senior Member Technical Staff Mentor Graphics Incorporation Indiana

2-6 years, preferably in implementing bus protocol BFMs or similar. Knowledge of C/C++ and exposure to verification environments (SV OVM, SystemC, Vera) is a plus. Knowledge of... more

Sep 03 Senior Member Technical Staff Mentor Graphics Indiana

2-6 years, preferably in implementing bus protocol BFMs or similar. Knowledge of C/C++ and exposure to verification environments (SV OVM, SystemC, Vera) is a plus. Knowledge of... more

Sep 02 Graduate Design Engineer - Implementation Middlesex Community College Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Sep 02 Graduate Design Engineer - CPU Middlesex Community College Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Sep 02 Graduate Design Engineer - Systems IP Middlesex Community College Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Sep 02 Graduate Design Engineer - Systems IP Artisan Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Sep 02 Graduate Design Engineer - CPU Artisan Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Sep 02 Graduate Design Engineer - Implementation Artisan Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Aug 31 Product Engineering SW Architect - Semi and System Software Wipro Technologies Portland, OR

Embedded SW, C++, SystemC/ TLM2/ Perl/ Python/ Basic Architecture concepts, SW processes?Basic ISA modeling / IP Modeling / Writing Tests / AutomationSOC Modeling ( Func / Cycle... more

Aug 25 Pre-Si IP Validation Job Intel Beaverton, OR

models for hardware components in C/C++, SystemC or equivalent languages - Experience in delivering IPs or integrating IPs working with internal and external customers Job... more

Aug 25 Engineering Lead - Contro.. UTC Aerospace Systems Windsor Locks, CT

and analysis using languages such as SystemC or UML, software requirements modeling and simulation-based verification, HIL and SIL verification testing, network performance... more

Aug 25 Software Development Engineer Job Intel Beaverton, OR

Skills: working/hands on knowledge of SystemC/ C++/ C hands on experience with Virtual Prototyping and System Level Design Flows Additional knowledge: knowledge of developing for... more

Aug 25 ASIC Engineer 3 Juniper Networks Sunnyvale, CA

experience. · Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills. · Must have good leadership/communication skills. · Networking experience is highly... more

Aug 23 Engineering Lead - Control Sys, Embedded Sys and/or Product UTC Aerospace Systems Windsor Locks, CT

and analysis using languages such as SystemC or UML, software requirements modeling and simulation-based verification, HIL and SIL verification testing, network performance... more

Aug 22 Engineering Lead - Control Sys, Embedded Sys and/or Product Architecture UTC Aerospace Systems Windsor Locks, CT

and analysis using languages such as SystemC or UML, software requirements modeling and simulation-based verification, HIL and SIL verification testing, network performance... more

Aug 21 Multiple Openings with Qualcomm--- Immediate Interviews Calsoftlabs-an Alten Group Company San Diego, CA

and supporting C++ and SystemC functional models for the Digital Hardware Team in ... environment at SystemC level - HW/SW co-verification - HLS tools such as... more

Aug 20 MTS ASIC/ Layout Design Engineer AMD Massachusetts

SV/VMM, SV, C++, SystemC, Vera, E)
• Mastery of a scripting language (Shell, Perl, Python, Ruby)
• Verification functional coverage using industry standard coverage analysis... more

Aug 15 Engineering Lead - Control Sys, Embedded Sys and/or Product Architecture United Technologies Windsor Locks, CT

and analysis using languages such as SystemC or UML, software requirements modeling and simulation-based verification, HIL and SIL verification testing, network performance... more

Aug 15 Engineering Lead - Control Sys, Embedded Sys and UTC Aerospace Systems Connecticut

and analysis using languages such as SystemC or UML, software requirements modeling and simulation-based verification, HIL and SIL verification testing, network performance... more

Aug 15 RTL Validation engineer Job Intel Santa Clara, CA

in object-oriented programming such as SystemC and SystemVerilog, assertion languages such as OVA, as well as verification coverage tools and matrices are required. Knowledge of... more

Aug 13 Mixed Signal Validation Job Intel Beaverton, OR

and validation -Working knowledge of C/C++/SystemC and other high level languages Job Category: Engineering Primary Location: USA-Oregon, Hillsboro Full/Part Time: Full Time Job... more

Aug 10 Audio Performance Simulation Architect Intel Folsom, CA

an Object Oriented Perspective Knowledge of SystemC, TLM, and modeling in general Enthusiasm to prototype and discard code as necessary Scripting An enjoyment of tinkering,... more

Aug 10 Senior Digital Design Engineer Job Intel Folsom, CA

- Experience with languages such as C/C++, SystemC, System Verilog, Perl, Specman e, Shell scriptin - Strong ASIC and/or SoC design experience - Experience with industry standard... more

Aug 09 Audio Performance Simulation Architect Job Intel Folsom, CA

an Object Oriented Perspective Knowledge of SystemC, TLM, and modeling in general Enthusiasm to prototype and discard code as necessary Scripting An enjoyment of tinkering,... more

Aug 05 Design Modeling Engineer-Temporary - Engineer III Mindlance San Diego, CA

advanced modeling methodologies in C++ and SystemC. You are expected to understand the ... for implementing and supporting C++ and SystemC functional models for the Digital... more

Aug 05 System Modelling E-solutions Portland, OR

and validating cycle-accurate IP models in SystemC/TLM 1. Integrate IP models in SOC ... infrastructure and peripheral IPs in SystemC · Experience in building virtual... more

Aug 04 Embedded System Engineer Net2source Portland, OR

and validating cycle-accurate IP models in SystemC/TLM Integrate IP models in SOC ... Skills: Good knowledge and experience in SystemC/TLM2 Expert in C++ and OOPs Knowledge... more

Aug 04 Engineer Circuit Design 3(14015703) Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. Northrop Grumman Corporation is a leading global security company providing innovative systems, products, and solutions in... more

Aug 04 Design Modeling Engineer Calsoftlabs-an Alten Group Company San Diego, CA

for implementing and supporting C++ and SystemC functional modelsfor the Digital ... -Design and verification environment at SystemC level -HW/SW co-verification -HLS... more

Aug 04 Engineer Circuit Design 3 Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. Northrop Grumman Corporation is a leading global security company providing innovative systems, products, and solutions in... more

Jul 30 System Modelling Architect Enterprise Solutions Portland, OR

and validating cycle-accurate IP models in SystemC/TLM Integrate IP models in SOC ... stacks on the VP Skills: Embedded SW, C++, SystemC/ TLM2/ Perl/ Python/ Basic... more

Jul 29 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of Science degree in Electrical or Computer Engineering with a minimum 9 years of relevant experience or 7... more

Jul 29 Master- or Bachelor thesis (f/m) in Engineering and Supply Chain IT - Adaptive SystemC based simulation engine Intel Nuremberg, PA

Engineering and Supply Chain IT - Adaptive SystemC based simulation engine. This ... itself. Content of the thesis is: Adaptive SystemC based simulation engine: -... more

Jul 28 Senior Application Engineer FV Mentor Graphics Indiana

‘e’, Vera, PSL, SystemC knowledge • Simulation/Verification using directed tests, constraint random testing, assertions and coverage driven verification methods • RTL and Gate... more

Jul 28 Senior Application Engineer FV Mentor Graphics Incorporation Indiana

‘e’, Vera, PSL, SystemC knowledge • Simulation/Verification using directed tests, constraint random testing, assertions and coverage driven verification methods • RTL and Gate... more

Jul 24 Analog EDA Application Engineer Texas Instruments Dallas, TX

MATLAB, Verilog, Verilog-A,, Verilog-AMS, VHDL, VHDL-AMS and/or SystemC). * Ability to setup and debug analog and mixed-signal simulations and analyze data in Analog Artist is... more

Jul 24 SIP Pre-Si Verification Engineer Intel California

Experience with software like C, C , SystemC advantage Experience with validation of interconnects/fabrics would be added value. Experience with System Verilog, OVM/Saola... more

Jul 24 System Modelling Enterprise Solutions Mountain View, CA

and validating cycle-accurate IP models in SystemC/TLM Integrate IP models in SOC ... Skills: Good knowledge and experience in SystemC/TLM2 Expert in C++ and OOPs Knowledge... more

Jul 24 ASIC Design Verification Viasat Marlborough, MA

experience * Experience with C++ or SystemC Our Marlborough office is an extension of our Carlsbad, California Engineering Center. The office provides a start-up feel with the... more

Jul 17 Modeling/ Virtual Platform Engineer Sage IT Portland, OR

5+ years of Experience in C/ C++/ SystemC based modeling design, validation ... test bench, test environment, development of SystemC test cases as well system regression... more

Jul 16 RTL Validation engineer Intel Santa Clara, CA

in object-oriented programming such as C , SystemC and SystemVerilog, assertion languages such as OVA, as well as verification coverage tools and matrices are required. Knowledge... more

Jul 14 SMTS ASIC/ Layout Design Engineer Amd | Seamicro Sunnyvale, CA

well as CUDA/OpenCL experience is a plus o SystemC based modeling experience could be useful as well • Expert level in C/C++ programming and Linux • Unix environment experience... more

Jul 10 Analog EDA Application Engineer Texas Instrutments Dallas, TX

MATLAB, Verilog, Verilog-A,, Verilog-AMS, VHDL, VHDL-AMS and/or SystemC). * Ability to setup and debug analog and mixed-signal simulations and analyze data in Analog Artist is... more

Jul 10 Instant Closure Need Pre-Silicon Engineer @ Simplion Technologies Milpitas, CA

PCIe, USB, SATA, MIPI etc ) or Memory Interfaces ( Flash, DDR, SDIO etc ) or SoC infrastructure blocks ( Bus Infrastructure, DMA etc ). Experience in emulation / systemc is a... more

Jul 10 Need Modeling/ Virtual Platform Engineer @ Simplion Technologies Portland, OR

2. 5+ years of Experience in C/ C++/ SystemC based modeling design, validation ... bench, test environment, development of SystemC test cases as well system regression... more

Jul 09 Mixed Signal Validation Intel Oregon

nd/or their equivalent -6mths industry experience in SOC/ASIC verification -6mths experience in post-si debug and validation -Working knowledge of C/C /SystemC and other high... more

Jul 08 Design Verification Engineer Amd | Seamicro Sunnyvale, CA

functional modeling using C++ and SystemC preferred • Familiarity with System Verilog and OVM/UVM preferred • Experience with build tools including make, version control, Perl, or... more

Jul 01 Pre-Si IP Validation Hillsboro, OR

models for hardware components in C/C++, SystemC or equivalent languages * Experience in delivering IPs or integrating IPs working with internal and external customers *Job... more

Jun 29 Software Development Engineer Hillsboro, OR

Skills: working/hands on knowledge of SystemC/ C++/ C hands on experience with Virtual Prototyping and System Level Design Flows Additional knowledge: knowledge of developing for... more

Jun 28 Software Development Engineer Intel Hillsboro, OR

Skills:working/hands on knowledge of SystemC/ C++/ Chands on experience with Virtual Prototyping and System Level Design FlowsAdditional knowledge:knowledge of developing for... more

Jun 18 Mixed Signal Validation Hillsboro, OR

and validation * Working knowledge of C/C++/SystemC and other high level languages *Job Category:* Engineering *Primary Location:* USA-Oregon, Hillsboro *Full/Part Time:* Full... more

Jun 13 Team Lead Verification Engineer Teradyne North Reading, MA

and ATE support. - Expert level C/C++, SystemC, System Verilog programming skills are required - Extensive experience with verification EDA tools with ability to optimize... more

Jun 12 Principal R&D Application Engineer Cadence Design Systems San Jose, CA

programming and system simulation using SystemC is a plus * Must have excellent written and verbal communication skills as well as good problem solving skills. * Able to travel 2... more

Jun 09 Senior Principal Analog Design Engineer Terran Systems San Jose, CA

with analog behavioral modeling a plus (SystemC, System Verilog, Matlab) ? Self driven, results -oriented individual capabile of working well with a very experienced and proven... more

Jun 05 Engineer Circuit Design 4 Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. EGPD2014Basic Qualifications: Bachelors of Science degree in Electrical or Computer Engineering with a minimum 9 years of... more

May 29 Analog Design Engineer Cybercoders Mountain View, CA

- Behavioral modeling with System Verilog, SystemC, Matlab and other languages - Worked in a Cadence or similar environment What's In It for You - Well-Funded, Exciting, and... more

May 29 Analog IC Engineer Cybercoders Irvine, CA

- Behavioral modeling with System Verilog, SystemC, Matlab and other languages - Worked in ... - Low power design - A / D Converters - SystemC - System Verilog - PLL - Matlab - High... more

May 29 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Communications Camden, NJ

proficiency in C/C++, VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired but not required. Knowledge of high-speed peripheral interfaces... more

May 26 Electrical Engineer - Consumer Electronics Survios Los Angeles, CA

experience with design verification using SystemC, SystemVerilog or similarExperience with verification and debugging tools such oscilloscope, multimeter, signal and spectrum... more

May 20 SW Engr, ESL Simulator Development Cadence Design Systems San Jose, CA

experience profile: * Experience developing SystemC and TLM2 based simulation or debug ... of debugging tools and techniques for SystemC Virtual Platforms is highly... more

May 20 Technical Director/Chip Architect Broadcom Irvine, CA

tools such as NS-2, Omnet++, SystemC is highly desirable **Country** US **State/Province** CA **City/Town** Irvine **Shift** 1st Shift - Day **Percent of Travel Required** 25% -... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

proficiency in C/C++, VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired but not required. Knowledge of high-speed peripheral interfaces... more

Apr 28 Verification Architect Compnova Hudson, MA

Expertise in C/C++ and systemC. Knowledge of Specman/e a plus. Knowledge of emulation and writing testbenches for emulation a plus. Excellent communication and team work skills. more

Apr 28 Pre- Silicon Verification-(252689) Compnova Santa Clara, CA

• Expertise in c/c++ and systemC. Knowledge of Specman/e a plus. • Knowledge of emulation and writing testbenches for emulation a plus. Excellent communication and team work... more

Apr 25 Sr Application Engineer Cadence Design Systems San Jose, CA

with a mix of SystemVerilog, SystemC/C/C++, Verilog & VHDL using industry ... SystemVerilog, VHDL, Verilog, C/C++, SystemC * Experience with debug of UVM * Ability... more

Apr 23 Lead Engineer Mentor Graphics Indiana

sure to ARM assembly language, ARM processor architecture, ARM Fast Models, QEMU are a plus. Exposure to Verilog/VHDL/System Verilog, SystemC and functional verification tools... more

Apr 23 Lead Engineer Mentor Graphics Incorporation Indiana

sure to ARM assembly language, ARM processor architecture, ARM Fast Models, QEMU are a plus. Exposure to Verilog/VHDL/System Verilog, SystemC and functional verification tools... more

Apr 18 Design Verification Engineer AMD Sunnyvale, CA

functional modeling using C++ and SystemC preferred • Familiarity with System Verilog and OVM/UVM preferred • Experience with build tools including make, version control, LSF,... more

Apr 08 Emulation Applications Engineer Mentor Graphics Fremont, CA

desirable. SystemC and C++ used in conjunction with chip design and verification highly desired. • Must have previous experience with industry emulation solutions, as well as... more

Apr 08 Emulation Applications Engineer Mentor Graphics Incorporation Fremont, CA

desirable. SystemC and C++ used in conjunction with chip design and verification highly desired. • Must have previous experience with industry emulation solutions, as well as... more

Apr 07 Principal Application Engineer Cadence Design Systems Austin, TX

environments utilizing SystemVerilog, e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience creating a Verification Plan and using verication management tools... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

ec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC, Scripting language Tools:... more

Dec 03 Lead Verification Engineer, SoC Cadence Design Systems Austin, TX

Formal (Assertion) Based Verification * SystemC, TLM1.0/TLM2.0 experience * ARM Processor knowledge * Digital Design experience * Other standard bus protocol knowledge (i.e. more

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