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Featured Job Postings from the Web
May 20 ASIC Digital Mixed Signal IC Design Engineer IT Consulting / Services Company Boston, MA

metropolitan area is looking for an ASIC/Digital Mixed Signal Design Engineer as ... ASIC/Digital Mixed Signal Design Engineer Qualifications: * At least 5+ years of RTL based... more

May 20 SSD Firmware Developer - Staff Engineer Job Seagate Shakopee, MN

SSD Firmware Developer - Staff Engineer - 123417 Seagate delivers advanced digital storage ... organizations with other engineers from ASIC Development, Electrical Integration,... more

May 17 Senior ASIC Design Engineer IT Consulting / Services Phoenix, AZ

ASIC / Digital Design Engineer as soon as possible! We are looking for candidates within t ... directly with the Hiring Manager. Senior ASIC Design Engineer Qualifications Include:... more

May 17 Senior Test Engineer (Inertial or Gyroscope Testing) Exclusive Recruiting Firm Los Angeles, CA

Senior Test Engineer. The Senior Test Engineer will develop test procedures and ... of MEMS transducer elements and CMOS ASIC signal conditioning and control circuits... more

May 17 ASIC Development Manager (ASIC Circuit Design) Exclusive Recruiting Firm Los Angeles, CA

a full-time ASIC Development Manager.The ASIC Development Manager will lead the ASIC ... (minimum MS) Experience -Minimum 5 yrs ASIC design -Managed an ASIC design, tapeout... more

May 17 Senior ASIC Engineer (Mixed Signal CMOS) Exclusive Recruiting Firm Los Angeles, CA

client of ours is seeking a full-time Senior ASIC Engineer. This position will be ... Senior ASIC Engineer will be working on new ASIC product definition, architecting and... more

May 17 Digital Application Specific IC Physical Design Engineer 5 Northrop Grumman Baltimore, MD

physical design of digital and mixed signal ASIC designs targeting deep submicron foundry ... static timing analysis, statistical static timing analysis, on chip variation timing... more

May 14 Sr. Firmware Engineer - ASIC / FPGA Emulex San Jose, CA

The Firmware Engineer who is excited by the prospect of building the next generation of ... Here, everybody counts. As a Firmware Engineer working at our office in San Jose or... more

May 02 RTL Verification / ASIC Design Engineers Sigma Consultants Group Hillsboro, OR

ASIC Design Engieer(s) 3) Design Automation Engineer(s) * Wewill consider all candidates ... Position: 3 ASIC Design - Structural design, synthesis,... more

May 01 Lead Application Engineer Cadence Designs Plano, TX

understanding of Physical Design and ASIC Timing Closure is a must - Previous usage of ... required - Thorough Understanding of Static Timing and Low Power Design Techniques is... more

May 01 Senior ASIC Digital IC Design Engineers IT Consulting / Services San Diego, CA

Diego, California is looking for a Senior ASIC / Digital Design Engineer (PMIC) as soon ... integration Senior ASIC Digital IC Design Engineer Qualifications Include: * 5-10+... more

Apr 29 Staff ASIC Design Verification Engineer Emulex Austin, TX

For the ASIC Design Verification Engineer who has impeccable analytical skills and ... everybody counts. www.emulex.com As our ASIC Design Verification Engineer your... more

Apr 15 SOC ASIC Designers Fortune 500 San Jose, CA

Multiple ASIC Design/Verification positions Hi We have multiple ASIC Design/Verification p ... of working experience. Requirement 3 MTS ASIC Design Verification Engineer... more

Feb 15 Sr Design Engineer , Physical Design Cadence Design Systems San Jose, CA

design and verification. Experienced with ASIC design flow, hierarchical physical ... Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis,... more

Jan 13 Staff Design Engineer, Physical Design Cadence Design Systems San Jose, CA

design and verification. Experienced with ASIC design flow, hierarchical physical ... Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis,... more

More Job Postings from the Web
May 21 ASIC VERIFICATION-MTS Design Engineer Advancement Massachusetts

PRIMARY PURPOSE: Provide technical expertise for execution on the functional verification strategy for next generation microprocessor designs. Maintain and enhance existing... more

May 21 DFT/Timing Principal IC Design Engineer Broadcom Santa Clara, CA

and implement the flow required to achieve Timing Closure in DFT mode Working with Test ... self-test flow experience Must have SI-aware Timing Analysis and Closure experience DFT... more

May 20 Staff ASIC Engineer JDS Uniphase Milpitas, CA

We are seeking a Staff ASIC Design Engineer to join our FPGA/ASIC Packet Portal team ... coding, simulation, verification, synthesis, timing closure, and silicon validation. more

May 20 Director of ASIC Engineering position in San Diego Alliance Search Group San Jose, CA

Director of ASIC Engineering ** This is a full-time/permanent position and you must be wil ... ASIC design team to generate plans for ASIC development and manufacturing,... more

May 20 Digital and ASIC Design Engineer Mso Technology Portland, OR

s, Integrated Circuits, Design, Engineering - Design and specify micro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate... more

May 20 Firmware Video Engineer - real-time, H.264, Video Compression Cybercoders Cupertino, CA

Firmware Video Engineer - real-time, H.264, Video Compression Firmware Video Engineer - ... Debug, Streaming Multimedia Firmware Video Engineer - RTOS, H.264, Video Compression,... more

May 19 ASIC Development Engineer Spec Writer (Entry Level) LSI Longmont, CO

pursue such future opportunities. An engineer filling this position would research ... - Verilog HDL - ASIC development - Static timing analysis Design research... more

May 17 Modem ASIC Design Engineer Tensorcom Carlsbad, CA

designers. Opportunities for exceptional ASIC engineers (digital design) to implement ... gate level synthesis and simulation, timing closure, power and signal integrity... more

May 17 physical design engineer (implementation of SOC/ASICs, Encounter) S & D Engineering Solutions Irvine, CA

COMPETENCY SUMMARY Place and route flow timing and SI closure synthesis timing ... treeCTS routing SI and timing closure Static Timing Analysis tools such as... more

May 17 Engineer - ASIC - New College Grad Job Seagate Longmont, CO

Engineer - ASIC - New College Grad - 121923 Seagate delivers advanced digital storage ... Longmont, CO is seeking an entry level ASIC engineer to join our team. Work in a small... more

May 17 ASIC Design Engineer (VLSI, DSP) Broadcom Irvine, CA

IO interfaces, integration, PnR, synthesis, timing closure, DFT. The candidate will be ... market - Analyze synthesis & STA (Static Timing Analyzer) results and give feedback to... more

May 16 Engineer, Staff ASIC Design Marvell Technology Group Aliso Viejo, CA

for the next-generation Marvell Ethernet PHY IC. Responsibilities include logic design, verification testcase development, synthesis, and timing convergence. Interaction with... more

May 15 ASIC Validation Engineer Infinera Sunnyvale, CA

ASIC Validation Engineer Job Description: * The successful candidate will contribute ... * 2 - 4 years of relevant experience in ASIC validation field. * Should have worked... more

May 15 Digital ASIC Designer (Recent Graduate) HP Careers Vancouver, WA

of BSEE/CE, MSEE/CE preffered with digital ASIC design experience. Individual with solid ... systems is desired. Knowledge of digital ASIC design methodologies and tools is... more

May 14 Digital ASIC Designer (Recent Graduate) HP Vancouver, WA

of BSEE/CE, MSEE/CE preffered with digital ASIC design experience. Individual with solid ... systems is desired. Knowledge of digital ASIC design methodologies and tools is... more

May 13 ASIC Design Engineer, STA Apple Cupertino, CA

position requires thorough knowledge of the ASIC design timing closure flow and ... in ASIC timing constraints generation and timing closure 2)Expertise in STA tools... more

May 13 Sr. ASIC/ Layout Design Engineer AMD Sunnyvale, CA

Routing and timing optimization, Fullchip Timing Closure (Static Timing Analysis) ), ... 5-8+ years of Industry experience in ASIC Design with relevant Physical Design... more

May 11 ASIC/FPGA Design Engineer (SMES) L-3 Communication Systems - East Camden, NJ

designand development team ASIC/FPGA Design Engineer (SMES) Description: o Candidates ... o Candidates will work with systems engineers to translate system requirements into ASIC/F... more

May 11 Sr. Asic Design Engineer Intel Hillsboro, OR

synthesis, auto-place and route, extraction, timing & reliability convergence, layout ... technical guidance to junior design engineer and mentoring them. Qualifications... more

May 11 Staff ASIC Design Engineer Intel Phoenix, AZ

? Develop timing flows, build fullchip timing models and drive timing closure across ... ? Experience in timing and power signoff methodology development, timing corners/modes def... more

May 10 ASIC Verification Specialist Xtremeeda USA Austin, TX

engineers with generalized expertise in ASIC Verification US Citizen Green Card ... functional verification of high complexity ASIC and SOC designs Develop and use... more

May 10 ASIC/FPGA Design Engineer (SMES) L-3 Communications Camden, NJ

design and development team ASIC/FPGA Design Engineer (SMES) Description: o Candidates ... o Candidates will work with systems engineers to translate system requirements into ASIC/F... more

May 10 ASIC Verification Engineer Hot Contract Opportunity! Triad Engineering Marlborough, MA

Job Reference Code 2663 ASIC Verification Engineer Hot Contract ... an immediate need for an ASIC verification engineer to contribute as part of a... more

May 10 ASIC Engineer Staff Juniper Networks California

optimize the physical design layout and fix timing issues. Work with the Verification team to verify your block. Show leadership and provide guidance to junior engineers. more

May 09 ASIC Backend Engineer Beyondsoft Santa Clara, CA

include: - Knowledge of the modern SoC ASIC design metholology. - Knowledge of the ... TCL scripting, etc. - Understanding of the timing constraint development and able to... more

May 09 Sr. ASIC/IP Design Engineer Apple Cupertino, CA

ASIC/IP Design Engineer Responsibilities ---------------------- Will be responsible for vi ... Industry exposure to and knowledge of ASIC/FPGA design methodology Excellent collaborate s... more

May 09 Senior Engineer, ASIC Rockwell Automation Mayfield Heights, OH

countries around the world. Senior Engineer, ASIC (Hardware) Position Summary **Please ... Our Senior Engineer, ASIC will be part of an ASIC design team responsible for verification... more

May 09 Digital Design Engineer (ASIC) - 5+yr exp - 879045576 San Diego, CA

879045576 Title: Digital Design Engineer (ASIC) Industry: Telecom Location: San Diego, Ca ... * formal verification (LEC) * Static Timing Analysis Additional Skills: (Not... more

May 09 Senior ASIC Development Engineer Videojet Technologies Beaverton, OR

Bringing the Next Generation of Innovation Closer: Whenever you view a web site, click a mouse, make a cell phone call, or turn on a TV you touch our work. As a world leader in... more

May 08 ASIC Digital Mixed Signal IC Design Engineer Kforce Technology Boston, MA

metropolitan area is looking for an ASIC/Digital Mixed Signal Design Engineer as soon as possible. We are looking for candidates nationwide willing to relocate to the Boston, MA... more

May 08 Sr. ASIC Design Engineer Synaptics Santa Clara, CA

for a hands-on, team oriented, Design Engineer with strong digital design ... In this role, the engineer will be responsible for the architecture, specification, and de... more

May 08 Sr. ASIC Verification Engineer Synaptics Santa Clara, CA

for a hands-on, team oriented, Design Engineer with strong digital design ... In this role, the engineer will be responsible for the architecture, specification, and de... more

May 08 Sr. ASIC Design Engineer Hirenetworks Raleigh, NC

or Cadence based synthesis and static timing closure Excellent written and oral ... Experience: 10+ years of experience in ASIC Design and Verification including team... more

May 08 ASIC Engineer (Security Design) - Staff Job Seagate Longmont, CO

ASIC Engineer (Security Design) - Staff - 123462 Seagate delivers advanced digital storage ... ever-evolving, on-demand world. Are you an engineer seeking an exciting opportunity to... more

May 08 Senior ASIC Design Engineer -Frontend FSA Fujitsu Sunnyvale, CA

Engineer for our Sunnyvale location. The Sr. ASIC Design Engineer will work in the Fujitsu ... * Experience in ASIC/COT design flow... more

May 07 Senior Design Engineer - Timing SiRF Technology Phoenix, AZ

definition of clock structures. Own Static-timing analysis, timing margins. Generate ... in ASIC timing constraints generation and timing closure. Hands-on experience on... more

May 07 Senior Staff Engineer ASIC Verification Western Digital Irvine, CA

functionality of HDC (Hard Disk Controller) ASIC at block level or chip level with advanced coverage driven methodologies using specman e or system Verilog UVM. * Work closely... more

May 07 SR. RF/Analog, Digital, Asics & Mixed Signal IC Designers Eta Devices Cambridge, MA

management, low-power digital ASIC design, high-speed digital ASIC design, IC verification Experience in the design of complex systems; desirable candidates will be comfortable... more

May 07 ASIC Logic Verification Engineer CompuCom Systems Marlborough, MA

computer components manufacturer seeking an Engineer capable to providing logic ... This individual will be performing ASIC verification based on architectural / micro-archit... more

May 06 FPGA / ASIC Verification Engineer Cisco Systems San Jose, CA

FPGA / ASIC Verification Engineer In this role of Verification Engineer you will be joinin ... Job Responsibilities: Participate in the specification and verification of FPGA / ASIC as... more

May 04 Senior ASIC Verification Engineer Confidential Client Cupertino, CA

Senior ASIC verification Engineers needed for a Silicon Valley-based optical networking ... wall here. In addition, the Verification Engineer will be making significant... more

May 04 Senior ASIC Validation Engineer Confidential Client Cupertino, CA

tasks around you? The Senior ASIC Validation Engineer is tasked with doing exactly -- automating the ASIC validation infrastructure for this optical networking company using your... more

May 03 Senior/Staff Graphics ASIC Hardware Design Engineer QUALCOMM Boxborough, MA

Experience should include Verilog/VHDL design, Synopsys synthesis, static timing analysis, ... * Experience should include Verilog/VHDL design, Synopsys synthesis, static timing analysi... more

May 02 Senior ASIC Design Engineer AMD Sunnyvale, CA

and Synthesis Active role in Static Timing analysis, floor-planning, IP selection ... especially with Synthesis flow, Static Timing Analysis, Floor-planning and I/O ring... more

May 01 Senior ASIC DFT Engineer Advantex Irvine, CA

Static Timing/Noise/Coupling Analysis related to all DFT modes or ATPG Must be able to gen ... Understanding of synthesis/timing closure concepts... more

Apr 30 Senior ASIC - DFT Engineer Clariphy California

experienceUnderstanding of static timing and crosstalk/noise ... NLINTSynthesis: Design Compiler*Static timing: Primetime** indicates the preferred... more

Apr 25 Verification Engineer(ASIC) Mavensoft Technologies Hudson, MA

-This individual will be performing ASIC verification based on ... Necessary Skills (Must Have): 1. ASIC verification and debug experience 2. more

Apr 23 ASIC Design Engineer MTS Level 2 Hughes Network Systems Germantown, MD

Design and development of Application Specific Integrate Chip. Establish and conduct simulations and performance testing. Document coding design, test procedures, and test... more

Apr 19 R&D Engineer, Sr Staff-Timing Analysis Synopsys Hillsboro, OR

who will design the next generation of timing, noise and variation analysis ... process variation impact on timing, timing optimization, IC design flows (ASIC... more

Apr 17 ASIC Engineering QUALCOMM San Diego, CA

Qualcomm Research ASIC group explores new ASIC architectures, circuits, and techniques ... tapeout. Knowledge of digital logic design, timing, schematics. Ability to communicate... more

Apr 17 ASIC Verification Design Consultant Silverlink Technologies San Jose, CA

Position: ASIC Verification Design Consultant Duration: 6 Months / Full Time Location: San ... Engineering with 10+ years of experience in ASIC Verification - Expertise in ASIC... more

Apr 13 ASIC Design Verification Engineer- New Verification Environments! Emulex Austin, TX

ASIC Design Verification Engineer- New Verification Environments! For the ASIC Design ... everybody counts. www.emulex.com As our ASIC Design Verification Engineer your... more

Apr 13 ASIC Design Engineer Altera San Jose, CA

As an ASIC Design Engineer, you will take charge of timing closure and physical design in ... including floorplanning, place-n-route, timing closure, noise/IR/EM analysis. *... more

Apr 13 Static Timing Analysis Engineer Inmata Solutions San Jose, CA

design team youll be the timing owner for ASIC blocks which will involve close ... achieving timing closure on deep submicron ASIC designs 2+ years experience in... more

Apr 12 ASIC Physical Design Engineer Idhasoft Hillsboro, OR

- ASIC backend -Timing Closure and/or Physical Design & electrical/reliability analysis, r ... effects. In-depth understanding of timing issues in gate-level and... more

Apr 11 ASIC Verification Engineer Comira Solutions Pittsburgh, PA

Job Description: 1. Design verification of highly integrated ASICs by developing and using state-of-art techniques for the design verification of complex SOC communications chips. more

Apr 11 ASIC Physical Design Engineer Comira Solutions Pittsburgh, PA

Timing closure/ECO of standard cell ASICs ... and timing closure for a process based ASIC on a current mainstream technology node (65nm, 40/45nm, 28nm). 2. Be familiar with... more

Apr 10 ASIC Design Sr Manager Juniper Networks California

to help change the world... Juniper ASIC ASIC is the differentiator starting from ... * Track record of successfully managed/lead multiple ASIC's from start to finish... more

Apr 04 Principal ASIC Analog Design Engineer Stec Santa Ana, CA

State Drive) controller embedded system ASIC designs. This will include IP ... requirements and standards Experience of ASIC high speed interface (SERDES) design... more

Apr 03 ASIC Design Engineer Kelly Services Santa Clara, CA

Title: ASIC Design Engineer Location: Santa Clara, CA Duration 6 - 12 mos You should possess a minimum of a Bachelor of Science in Electrical Engineering or Computer Engineering... more

Mar 29 ASIC Design Engineer (Frontend) Ostendo Technologies Carlsbad, CA

an experienced ASIC engineer to join the ASIC design team to develop architecture and ... ASIC and FPGA experience * Experience in ASIC methodologies and tools * Experience in... more

Mar 29 Static Timing Analysis Engineer Samsung San Jose, CA

As a member of ASIC/SoC design team, you'll be the timing owner for ASIC blocks which will ... achieving timing closure on deep submicron ASIC designs 2+ years experience in... more

Mar 29 ASIC Design Engineer Brocade Communications Systems San Jose, CA

in design/verification of complex networking ASIC/FPGAs. Individual will be working with ... implement block level rtl, synthesis, and timing Block level verification: reference... more

Mar 26 ASIC Verification Flow Engineer Collabera Colorado

Opportunity for a senior ASIC Engineer to contribute to verification of digital cores for ... Responsibilities: Setup/run ASIC verification tools including Spyglass, LEC, 0-in, CDC .. more

Mar 26 ASIC DSP Design Engineer Applied Micro Circuits Sunnyvale, CA

as FIR & IIR filter, echo cancellation, FFT, timing recovery, Viterbi, error correction decoders such as LDPC or RS. * System Verilog, Matlab and C experience for verification is... more

Mar 23 ASIC Engineer General Dynamics Bloomington, MN

Key Responsibilities The Advanced ASIC Engineer is Responsible for definition, ... The Advanced Engineer- ASIC position requires a bachelors degree in in FPGA/ASIC related V... more

Mar 23 ASIC Design Engineers, FPGA, Communications. 6-month contract Accurit Staffing Downingtown, PA

Experience synthesizing and closing timing of designs is of great importance. ... the product in development. Contract Design Engineer Sunnyvale, CA 94086 My client... more

Mar 19 Staff ASIC Design Engineer SanDisk Milpitas, CA

design, verification, and documentation for ASIC development. Determines architecture ... design to synthesis, place and route, and timing and power use. Analyzes equipment to... more

Mar 13 ASIC Development Engineer - Spec Writer (Entry Level) LSI LOGIC Longmont, CO

Requisition Number: 12-8690 Job Title: ASIC Development Engineer - Spec Writer (Entry ... - Verilog HDL - ASIC development - Static timing analysis Design research... more

Mar 10 Real Time Embedded Development Engineer - C, Automotive Column Eng Southfield, MI

ur customer requires an embedded development engineer with at least 5years experience ... of assembly languages. Software Engineer Specific Duties: Document, analyze... more

Mar 08 ASICs Engineer, San Jose Fremont Consulting Elk Grove, CA

opportunities @fremontflash Sr. Applications Engineer (DIMMS, Memory Modules), San Jose, ... Be part of the next generation of ASIC innovations! ESSENTIAL REQUIREMENTS:... more

Mar 06 ASIC Design Engineer Abraxas Fort Meade, MD

ASIC/SoC/FPGA Lead Design Engineer Clearance: Must be eligible for US Government security ... synthesis, static timing analysis, DFT, ASIC vendor sign-off methodologies. Knowledge... more

Mar 05 ASIC Physical Design Engineer Beaverton, OR

validation, tool is Conformal), and timing analysis PV (tool is primetime) * ... layout edits, auto place and route, timing analysis, functional equivalency... more

Mar 01 Sr. ASIC Verification Engineers Terran Systems Sunnyvale, CA

Candidate will also assist where needed on various ASIC design assignments {chip and/or FP ... VERILOG, HDL, ASIC VERIFICATION, VERIFICATION ENGINEERING, TIMING... more

Jan 09 ASIC SoC Timing Engineer- The Bay Tara Technical Solutions San Jose, CA

ASIC SoC STA- The Bay Develop, own and enhance the full chip Timing Constraints for a ... (tcl/primetime etc.)Develop or enhance timing related scripts for constraints... more

Dec 19 MTS ASIC Design Engineer Cameron Resources Group Orlando, FL

an ASIC Design Engineer, you will: Develop ASIC architecture and micro-architecture ... test cases, and test benches Synthesis and Timing methodology Develop code for embedded... more

Dec 14 ASIC CAD/EDA Engineer TS SCI Full Scope Polygraph Design Staffing Fort Meade, MD

ASIC CAD/EDA Engineer Top Secret SCI Full scope or Lifestyle Polygraph Location: FT Meade, ... position for a well-rounded ASIC CAD/EDA Engineer. Qualifications: Candidate must... more

Nov 30 Senior Staff Engineer, SSD ASIC Development 63241028000000 Ssd Eng San Jose, CA

and power specifications, and identify timing solutions. - Perform verification ... circuits, and perform place-and-route and timing analysis of modules. - MS EE,... more

Sep 28 ASIC Design Engineer - Timing Terran Systems Santa Clara, CA

time requirement for a Design Engineer with Timing Closure experience. Please go through ... experience in owning and developing timing constraints for complex multi-clock... more

Sep 26 ASIC/Digital Design Engineer Executive Recruiting Associates Shelbyville, KY

ASIC/Digital Design Engineer Develops, designs, verifies, and documents ASIC/FPGA/CPLD dev ... Salary Range 64K 98K ASIC/Digital Design Engineer Develops, designs, verifies, and d... more

Sep 23 SENIOR ASIC TIMING ENGINEER NVIDIA Santa Clara, CA

SENIOR ASIC TIMING ENGINEER #1428892 In this role you will be responsible for developing ... expertise and experience in full-chip Static Timing Analysis, timing constraints... more

Sep 12 ASIC and/or FPGA Design Engineer with Security Clearance 2020itservices Fort Meade, MD

We have a need for an ASIC Design Engneer Engineer in Ft. Meade, MD. The job description ... nancy@2020itservices.com 310-543-1043 (work) ASIC and/or FPGA Design Engineer Multiple... more

Jul 02 ASIC Design Engineer Cross Creek Systems Santa Clara, CA

work with the physical design team to close timing and area goals. Requirements: BSEE required, MSEE preferred Minimum 7-10 years experience in design and development of complex... more

Jun 22 SR. ASIC TIMING ENGINEER NVIDIA Santa Clara, CA

SR. ASIC TIMING ENGINEER #1347254 - Timing signoff and convergence of large-scale ... timing constraints generation, physical/timing convergence, and ECO implementation. -... more

Jan 02 JR ASIC ENGINEER George Olivas San Jose, CA

simulation & verification designs * ASIC test and debugging Qualifications: * Requires a MSEE (PhD preferred) or equivalent experience * 2+ years of hands-on logic design... more

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