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Oct 06 Systems Verilog Engineer Tekpartners, A P2p Company Hillsboro, OR

test benches and functional tests in system Verilog. • Prepare specifications, ... Verilog, System Verilog, System C, using OVM/UVM methods. • Knowledge of Perl, Python... more

More Job Postings from the Web
Oct 21 RF Engineer-San Jose CA-Full Time IDC Technologies San Jose, CA

Writing/maintaining behavioral real number Verilog models of RF/analog blocks; Writing ... working with System Verilog and UVM; verifying mixed signal chips,... more

Oct 21 ASIC Verification Engineer (TX or NC) Technical Link Austin, TX

verification experience (System Verilog, Verilog) - Familiarity with industry ... with MESI cache protocols on a coherent system bus ASIC Verification, OVM, AMBA, IP... more

Oct 21 Digital Verification Engineer Nxp Semiconductors Tempe, AZ

verify logic designs, and building a System Verilog constraint driven testbench. This position requires excellent communication and problem solving skills. At least 5 years of... more

Oct 21 Lead Design Verification Electrical Engineer Insiderjobboard.com Vancouver, WA

the functional verification of ASICs using System Verilog and UVM methodologies. She/he ... ASIC verification infrastructure in System Verilog and pref Specman-e Hands-on... more

Oct 21 Verification Engineer Job Yoh Mesa, AZ

- Experience with Verilog and VHDL - UVM/OVM experience - Expert in debugging complex mixe ... Embedded design experience is preferred - System Verilog Experience is preferred -... more

Oct 20 Verification Engineers Novus Resources Raleigh, NC

  System Verilog, OVM/UVM, Functional Coverage, bus verification experience is a bonus ... fixes and feature development on complex system bus with cache coherency. Looking for... more

Oct 20 Junior Graphics Emulation Execution Engineer Apple Austin, TX

report status * Participate in debug of system by capturing waveforms and writing ... languages are C, Perl, Ruby, System Verilog) Graphics knowledge a plus; 3D... more

Oct 20 FPGA/ASIC Engineer General Dynamics Scottsdale, AZ

BSEE/MSEE/BSCS/MSCS or Equivalent Strong proficiency in SystemVerilog, Verilog, VHDL, C/C+ ... design verification using System Verilog. Additional preferential skills are Verilog... more

Oct 20 Principal/Sr. Principal RTL Verification Engineer (Processor) Applied Micro Circuits Sunnyvale, CA

environment development using System Verilog based methodologies (OVM/UVM) * ... assembly tests * Experience using the HDLs (Verilog, System Verilog) * Experience using... more

Oct 20 Sr Design Verification Engineer Bhi Energy |sun Technical Austin, TX

HDLs (e.g. Verilog, VHDL) and HVLs (e.g. System Verilog/OVM, UVM, AVM, Vera, e) ... models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing... more

Oct 20 SOC Design Verification Engineer San Diego, CA

and assertion languages RTL VHDL Verilog System Verilog System Verilog Assertions SVA Vera e Specman etc o Knowledge of SOC ARM processor AMBA bus DDR or peripherals is preferred... more

Oct 18 ASIC Verification Engineer CAE Recruiters Lowell, MA

languages: o working knowledge of verilog is a must; system-verilog is a plus • Working knowledge of C programming; C++/OO coding principles a plus • Scripting and automation... more

Oct 17 VLSI Verification Engineer Prism IT Folsom, CA

to drive IP level verification using System Verilog OVM b Activities include verification environment understanding development enhancements c Ability to work on Functional Low... more

Oct 17 FPGA Engineer - Quant Prop Trading Firm Selby Jennings Houston, TX

FPGA architecture design in VHDL and/or Verilog Experience with FPGA connectivity through ... science subject Experience writing system Verilog for synthesis and/or simulation... more

Oct 17 ASIC Architect (Senior / Principal) 1 Ericsson San Jose, CA

other functional block Write up the system architecture specification that base on the ... design Strong knowledge of Verilog/System-Verilog for implementation Good Network... more

Oct 16 Engineer, Senior Staff Verification Results Center Austin, TX

in design verification with System Verilog and UVM. Knowledge of other verification disciplines like Emulation, FPGA is a big plus. Must experience with both block level and... more

Oct 16 Engineer, Senior Staff Verification Marvell Austin, TX

in design verification with System Verilog and UVM. Knowledge of other verification disciplines like Emulation, FPGA is a big plus. Must experience with both block level and... more

Oct 16 Verification Engineer Tekpartners, A P2p Staffing Company Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... High level verification languages (OVM/UVM/System Verilog) Strong embedded design... more

Oct 15 Software Engineer I F5 Networks Spokane, WA

Work with TCP/IP networking system architects to understand the system level perspective a ... skills. Desired Qualifications System Verilog design and verification experience. more

Oct 15 Verification Engineer Evo Phoenix, AZ

REQUIREMENTS : EXPERT in HDL development (Verilog and VHDL) both in design and ... high-level verification languages (OVM/UVM/System Verilog) Strong embedded design... more

Oct 15 Senior ASIC/Layout Design Engineer (ASIC Verification Engineer) INF-102 Infinera Sunnyvale, CA

Write complex test bench components using SystemVerilog and UVM. Develop tests to ... of test benches and tests using System Verilog and verification methodologies such... more

Oct 14 Palladium Engineer : Palladium, FPGA, VHDL, Verilog Xpeerant Raleigh, NC

s of industry experience. FPGA based emulation with direct Palladium experience required. Excellent verbal and documentation skills Experience: Verilog and/or VHDL, System Verilog... more

Oct 14 Verification Engineer - 7942 eTech Resources Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... High level verification languages (OVM/UVM/System Verilog) :Strong embedded design... more

Oct 14 SENIOR DESIGN ENGINEER Judge Group San Jose, CA

Coding of designs and algorithms in Verilog and/or C Complete design cycle of simulation, ... *Good knowledge of verification methodology- *System Verilog experience - Salary:... more

Oct 14 SoC Verification Engineer : C/C++, TCP, DMA, DDR, AMBA Xpeerant Raleigh, NC

of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++ - Must have hands-on ... -Extensive UVM/System verilog skills, as well as exposure to DDR, I2C, AMBA, and PCIe test... more

Oct 14 Verification Engineer III (3867) Randstad Technologies - New Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... level verification languages (OVM/UVM/System Verilog) •Strong embedded design... more

Oct 14 Verification Engineer II US Tech Solutions Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... High level verification languages (OVM/UVM/System Verilog) Strong embedded design... more

Oct 14 Digital Verification Engineer Cyient Raleigh, NC

understanding of Object Oriented System Verilog principles including OVM or UVM. ... OVM or UVM (or at least VMM), verification (systemverilog, ovm/uvm/vmm, random... more

Oct 13 Senior Software Engineer - Simulation Library Development Xilinx San Jose, CA

simulation models in Verilog/VHDL/System Verilog. In this role, the candidate will ... new behavioral (VHDL, Verilog, System Verilog) and Secure IP models(encrypted... more

Oct 13 Lead Digital Design Engineer Texas Instruments Dallas, TX

synchronous digital skills. • Verilog or VHDL RTL development experience • Simulation ... Knowledge of System verilog, constrained random and assertion based verification... more

Oct 13 Advanced Memory Systems RTL Lead Engineer Job Micron Boise, ID

will include working with the System Architecture team to specify the ... have: - Proficiency with Verilog, and/or System Verilog, Linux OS, and associated... more

Oct 13 Pre-Si Verification engineer Classifiedads.com Santa Clara, CA

Scoreboard. * 7 years' experience working in System-Verilog OVM, since most of the VIP collaterals is developed in SV-OVM. * The candidate should be able to work independently... more

Oct 13 Engineer: Verification - III Experis Chandler, AZ

REQUIRED EXPERIENCE/SKILLS: BSEE degree Expert in HDL development (Verilog and VHDL) both ... High level verification languages (OVM/UVM/System Verilog) Expert in debugging complex... more

Oct 11 Sr Principal Electrical Engr with Security Clearance Raytheon El Segundo, CA

the development of OVM/UVM and System Verilog Assertion based training material, ... and/or Altera FPGAs. * Experienced with UVM, System Verilog and Assertion Based... more

Oct 10 Lead Electrical / System Engineer GE Billerica, MA

The product development team is seeking an experienced Lead Electrical / System Engineer t ... Familiarity with FPGA design including Verilog/System Verilog Familiarity with... more

Oct 08 ASIC Verification Sage IT Folsom, CA

System Verilog OVM/UVM, Good experience in System Verilog OVM/UVM based verification environment development, Sound understanding of Random and constrained random-verification... more

Oct 08 ASIC/SoC Design Verification Engineer (CPU Start-up) Quantum Solution Santa Clara, CA

verification, coverage driven verification, system & architectural compatibility ... large complex SoC * Hands on experience with System Verilog, NTB/VERA, SPECMAN, C/C++ and... more

Oct 08 Senior Pre-Silicon Validation Engineer Intel California

not limited to: * Designing and debugging SystemVerilog-based verification testbenches ... is highly desired - Proficient in Verilog / System Verilog - Deep experience in... more

Oct 08 Staff Design Engineer Mainz Brady Group San Jose, CA

knowledge of verification methodology System Verilog experience Are you available? Please ... httpwww.mbg.commobileapps Verilog AND "staff design engineeer" AND... more

Oct 08 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

implementing, debugging, and closing SystemVerilog functional coverage groups. ... experience Candidate SHOULD also have system verilog test bench experience. We need... more

Oct 06 Senior Staff Digital Design Engineer Fusion408 San Jose, CA

* Architecture of Digital Filters * RTL Design using Verilog/System Verilog * Top-level Synthesis &Static Timing Analysis (STA) * Digital Design for Ultra-Low Power applications *... more

Oct 02 Principal Engineer Leading Manufacturer of Computer Hardware Santa Clara, CA

of architectural specification documents, system level models, complex circuit design, ... with the VCS, Vera verification language, System Verilog, objected-oriented... more

Oct 02 Digital Design Engineer Cei Group Tempe, AZ

is Mandatory Must have expert knowledge of Verilog Implementing test modes communicate ... 5 yrs of experience Knowledge of System Verilog Cadence NcSim Designing and... more

Oct 02 Software Engineer / FPGA Design Engineer / Verilog Horizontal Integration San Jose, CA

of logic fundamentals Excellent knowledge of Verilog Capable of writing ... in statistical methods Good knowledge of verification methodology System Verilog... more

Sep 30 Principal SoC Verification Engineer Hitachi Global Storage Technologies San Jose, CA

and consumer electronics and automotive system manufacturers to store the avalanche of ... verification - Proficient in Verilog, System Verilog, experience using... more

Sep 30 Contract Staff Design Engineer Horizontal Integration San Jose, CA

of logic fundamentals Excellent knowledge of Verilog Capable of writing ... Good knowledge of verification methodology System Verilog experience Horizontal... more

Sep 25 Intern - IC Design (Spring 2015) Broadcom Andover, MA

verification test plans - coding in verilog / system verilog / perl - interact with design and verification team - code coverage and the review process - verification sign off -... more

Sep 24 Lead Design Verification Engineer Oracle Santa Clara, CA

high performance SOC - Develop & maintain System Verilog testbenches - Develop & ... Architecture • Experience coding Verilog, SystemVerilog and one of UVM/OVM/VMM •... more

Sep 23 Functional Verification Engineer - Pre-Silicon: 234296 Core-tech Santa Clara, CA

System Verilog OVM/UVMc. Good experience in System Verilog - OVM/UVM based verification ... architectureb. Creating test scenarios(System Verilog OVM)c. Work with RTL teams to... more

Sep 22 New Graduates 2015 - ASIC Verification Engineer –VEJE65 Cavium Marlborough, MA

Strong experience using C++ and Verilog/VHDL and PERL/Python ... Knowledge of semiconductor design verification techniques and System Verilog/UVM is desira... more

Sep 22 SoC Verification Engineers Calsoftlabs Raleigh, NC

have experience in System Verilog and either UVM (preferred) or OVM. 3+ years of ... chip, sub-system and/or blocks. You will define chip level verification strategies,... more

Sep 19 Verification Engineer, Cache- Eng II(OVM/UVM) Collabera Raleigh, NC

Skills / Experience: System Verilog, OVM, UVM, Object Oriented Programming, power experien ... Engineering or equivalent experience System Verilog, OVM, UVM, Object Oriented... more

Sep 18 Staff ASIC Verification Engr Job SanDisk Milpitas, CA

in different languages (C, C++, System Verilog) - Self-starter, Team player - Flash Memory and storage experience is preferred - Knowledge in protocols such as ONFI, UFS, PCIE,... more

Sep 17 New Grad - ASIC Design Engineer Viasat Cleveland, OH

logic designs with System Verilog • Experience in the design and verification of ... design verification of Verilog code in satellite and optical communications equipment. You... more

Sep 16 Principal ASIC Design Engineer Fortinet Technologies Sunnyvale, CA

Altera/Xilinx FPGA;· Participating system/board level bring up, debugging and ... knowledge;· Knowledge of System Verilog and UVM verification methodology;· Highly... more

Sep 11 Intern: ASIC Engineer Juniper Networks Sunnyvale, CA

or Computer Science * Strong Verilog, SystemC or C/C++, Perl/shell skills. * ... Perl or Python scripting experience. * System Verilog would be a plus but not necessary... more

Sep 10 R&D Engineer, Staff Synopsys Hillsboro, OR

to Verilog/VHDL. · Exposure to System Verilog, UVM, VMM or OVM · Knowledge of IC Design flows. · Unix, Perl and Tcl Scripting Knowledge. · Knowledge of SATA/PCIE protocol would be... more

Sep 09 C++ and System Verilog/UVM Engineer Hire IT People Marlborough, MA

Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. more

Sep 06 Electrical Engineer Sr Lockheed Martin Orlando, FL

skills. Familiarity with video system design, synchronization, image ... Experience with Verilog, C/C++, MathLab/Simulink, System Verilog languages; Synopsis Synpl... more

Sep 05 Senior Engineer, FPGA Design CSR Cambridge, MA

HW background · Proficient in System Verilog · Competent in digital design for ... equivalent qualification) · System and architectural design · Writing of design... more

Aug 23 Sr Electrical Engineer - ASIC/FPGA Rockwell Collins Iowa

of RTL blocks using VHDL or System Verilog. Applicants must be capable of obtaining ... functional coverage, SystemVerilog. â?¢ ASIC / FPGA lab validation with advanced lab... more

Aug 21 SoC Verification Eng Calsoftlabs-an Alten Group Company Raleigh, NC

if you do not have experience in System Verilog and either UVM (preferred) or OVM. 3+ ... verification effort of a complex chip, sub-system and/or blocks. You will define chip... more

Aug 21 SOC Verification Engineer Dbsi Services Raleigh, NC

all necessary tools and scripts to enable system-level testing in an automated fashion. ... of HVLs(VERA/e/System Verilog), HDLs(Verilog/VHDL), C/C++ Must have hands-on... more

Aug 20 Asic Engineer 3 Juniper Networks Westford, MA

plans, specifications and designs of UVM / System Verilog Based test benches. You will ... bench, drivers, monitors, scoreboards in System Verilog Create the test suites,... more

Aug 14 Sr Electrical Engineer-Asic/fpga Rockwell Collins Cedar Rapids, IA

of RTL blocks using VHDL or System Verilog. Proficiency using ASIC and/or FPGA ... constrained random, functional coverage, SystemVerilog) ASIC / FPGA lab validation... more

Aug 14 Engineer, Digital IC Design Marvell Technology Group Santa Clara, CA

to tape-out . Familiar with ARM SOC embeded system and AMBA. . Understanding of DDR, ... and NVMe would be a plus. . Understanding of System Verilog would be a plus . more

Aug 14 ASIC Developer Braves Technologies Irvine, CA

tes who are CAP Exempt and have a valid stamped H1B visa shouldapply.Location: Irvine CA. ASIC DeveloperSkills Required: ASIC Must have experience in System Verilog/ Verilog,OVM,... more

Aug 12 Digital Design and Verification Engineer On Semiconductor Plano, TX

• Verification of system IP at the sub-system level o Producing a detailed ... in either Verilog or VHDL (Verilog preferred) • Verification experience with one of... more

Aug 05 Senior Member Technical Staff Mentor Graphics Incorporation Indiana

verification • Required: Strong Verilog/System Verilog Experience, Strong C++ PLI experience, Good Assembly understanding, Some bus protocol understanding ( e.g. PCI, AXI ) •... more

Aug 05 Design Modeling Engineer-Temporary - Engineer III Mindlance San Diego, CA

knowledge of HVLs( System Verilog ), HDLs ( Verilog/VHDL/SystemVerilog), C/C++, SystemC ... - Verilog, system Verilog or vhdl - Experience in ASIC/System verification, processor veri... more

Jul 24 Hardware Verification Engineer (MemC/DDR PHY experience) (E1924523) QUALCOMM Austin, TX

experience *LI-SRC Keywords System Verilog, UVM, Verification, IP Verification, DDR, Memory Controller You will need to login into your profile to apply for this job. If you are a... more

Jul 14 DFX validation engineer Intel Israel, PR

validation environments based on System Verilog and work with RTLdesigners and post ... verification/validation methods, Specman language, SystemVerilog, DFX design &... more

Jul 06 FPGA ENGINEER Judge Group Atlanta, GA

of FPGA code including Verilog and/or System Verilog hardware description ... methods using Verilog, and/or System Verilog hardware description language... more

Jul 01 IC Design Verficiation Engineer Avago Technologies Allentown, PA

processor products. The candidate will use SystemVerilog, Verilog and other Unix ... using behavioral simulation using System Verilog, VMM or UVM methodologies. *... more

Jun 30 Digital Design Engineer Inphi Thousand Oaks, CA

implementing RTL designs using Verilog/SystemVerilog; implementing verification test ... of digital and mixed-signal circuits; Verilog or System Verilog to verify functional... more

Jun 20 Design Verification Engineer 2 AMD Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 17 FPGA Engineer III - Bothell Sonosite Washington

(VHDL, System Verilog, System C or C/C , scripting in Bash, Python, Perl, or Tcl). ��� Experience with ISO, FDA, or other regulated product development environments is a plus. ���... more

Jun 13 Design Verification Engineer 2 Amd | Seamicro Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 10 Digital Design Engineers (AMRD356-357) Fortinet Sunnyvale, CA

of latest Verilog and System Verilog syntax constructs • Experience with ... understanding of simulation and synthesis implications of various Verilog RTL... more

Jun 09 Sr Staff Engineer Seagate Shakopee, MN

utilizing Unix, Linux, Synopsys Tools, and Verilog. Experience running large scale ... Experience designing in Verilog and/or System Verilog... more

Jun 06 Memory Subsystem Design Engineer Talarience Folsom, CA

and/or software architects to develop system models, evaluate memory system ... models and evaluation tools in C/C++, system Verilog and similar environments. more

May 31 Engineer, ASIC Design Verification Results Center Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 30 Engineer, ASIC Design Verification Marvell Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 20 IC Verification Engineer eTech Hi Simi Valley, CA

candidate will have experience using System Verilog, Specman e, Vera or System C) ... * Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.If interested... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired ... a plus. Knowledge of ARM microprocessor-system is a big plus. Very strong... more

Apr 23 Lead Engineer Mentor Graphics Indiana

e to ARM assembly language, ARM processor architecture, ARM Fast Models, QEMU are a plus. Exposure to Verilog/VHDL/System Verilog, SystemC and functional verification tools like... more

Apr 09 SENIOR VERIFICATION ENGINEER NVIDIA Santa Clara, CA

methodologies. - Experience with memory sub system verification is highly desirable. - ... highly desirable. - Expertise in System Verilog. - Scripting knowledge. - Good... more

Apr 07 Principal Application Engineer Cadence Design Systems Austin, TX

e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience ... Languages: SystemVerilog, Specman e, VHDL, verilog Methodologies: Preferable experience in... more

Mar 25 Analog Behavioral Modeling Engineer Recruiting Engine (mls) San Diego, CA

testing. Experience with Modelsim, NC-Verilog, VCS or similar digital logic ... Experience with Verilog and/or System Verilog Experience with Cadence-AMS or similar AMS m... more

Mar 24 Digital Design Engineer Google Mountain View, CA

the lowest levels of circuit design to large system design and see those systems all the ... * Proficient in RTL / Logic / Verilog / System Verilog. * Successfully delivered... more

Mar 19 Verification Engineer Altera San Jose, CA

in programmable logic solutions, enabling system designers and semiconductor companies ... methodologies (such as UVM, OVM, System Verilog, constrained-random stimulus... more

Feb 13 Principal Verification Engineer Aba Search San Jose, CA

and development and modeling using UVM, SystemVerilog, Verilog. EXPERIENCE o ... verification languages OVM/UVM/System Verilog/C++ o Expertise in putting... more

Feb 12 Design Verification Engineer Commnexus Santa Clara, CA

programming ability in C, C++, System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Feb 05 Video Codec Engineer Extron Electronics Raleigh, NC

* Experience in C/C++, Verilog/VHDL, System Verilog/C, Perl/Python ... and manufacturer of professional AV system products. Extron products are used to... more

Jan 08 Sr. R&D Engineer Real Intent California

of the following fields: GUI, Verilog/System Verilog/VHDL Compilation, Synthesis ... and verification flow, working knowledge of Verilog, VHDL, and SystemVerilog... more

Jan 07 ASIC Verification Engineer Systel Santa Clara, CA

VMM, OVM, UVM Development will be done System Verilog Develop test plans, execute and ... building Verification environments using SystemVerilog, VMM/OVM/UVM Past experience in... more

Jan 07 Senior Verification Engineer Aba Search San Jose, CA

o Hardware modeling using UVM, Verilog, System Verilog or C/C++ o 6 + years of ... functional coverage o Expertise in System Verilog, OVM/UVM or Vera based tools o... more

Dec 31 FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL Darwin Recruitment Newport Beach, CA

FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL FPGA/ASIC Designer - Darwin Recruitme ... or equivalent academic qualification. System Verilog or Specman Cadence E... more

Dec 02 Verification Engineer Cypress Semiconductor Colorado Springs, CO

Skills Digital Verification using System Verilog Experience using OVM or UVM, ... Experience Digital Verification using System Verilog Experience using OVM or UVM,... more

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