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Sep 17 Postdoctoral Scholar Pennsylvania State University Pennsylvania

sensor process; C/C++/C#/Java; Python; ROS; Verilog or SystemVerilog; VHDL; Open CV and Open CL; and Linux. Candidate selected may be subject to a government security... more

Sep 16 Principal ASIC Design Engineer Fortinet Technologies Sunnyvale, CA

Altera/Xilinx FPGA;· Participating system/board level bring up, debugging and ... knowledge;· Knowledge of System Verilog and UVM verification methodology;· Highly... more

Sep 16 Graphics Software Engineer Apple Austin, TX

with scripting, DPI, Verilog/VHDL, Specman/System Verilog, design verification methodology and tools a plus * Team leadership experience a plus * Excellent communication skills... more

Sep 15 Design Verification Engineer Symphonyteleca Hudson, NH

Work with Verilog/System Verilog/ C Programming/scripting languages/ logic analyzers/ osci ... Microcontrollers Embedded Software Verilog System Verilog C Programming Scripting... more

Sep 15 Mixed-Signal Circuit Functional Verification Classifiedads.com Santa Clara, CA

and HDL testbench creation using Verilog/System Verilog/VHDL is beneficial ... Behavioral Modeling Languages: Verilog-HDL, Verilog-A, Verilog-AMS, System Verilog * 2+... more

Sep 15 Junior FPGA Engineer Request Technology-stephanie Baker Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit/system testbenches Test ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Sep 15 FPGA Engineer Request Technology-anthony Honquest Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit/system testbenches Test ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Sep 15 ASIC Verification Engineer 4120R Embedded Resource Group San Jose, CA

Required Expert level UVM System Verilog At least 2-3 years of UVM projects Desired Experience with embedded software is a plus SSD PCIe NVMe - Non Volatile Memory express is plus... more

Sep 14 Power Electronics Design Engineer Newtown Solutions Fargo, ND

Verilog and System Verilog (Verilog Preferred) • Test Bench Design and simulation methodology. (Xilinx and Modelsim tools preferred). • DDR, DDRII, DDRIII, mDDR, mDDRII, NAND... more

Sep 14 VLSI Tech Lead - Verification Wipro Chandler, AZ

Methodology - OVM(Mandatory) System Verilog - SV(Mandatory) VLSI HVL VerificationAs a Lead, you are responsible for managing a small team of analysts, developers, testers or... more

Sep 13 FPGA/ASIC Engineer General Dynamics Arizona

BSEE/MSEE/BSCS/MSCS or Equivalent Strong proficiency in SystemVerilog, Verilog, VHDL, C/C+ ... design verification using System Verilog. Additional preferential skills are Verilog... more

Sep 12 Verification Engineer Everest Consultants Santa Clara, CA

desirable. - A strong background specifying and developing random test environments is also desired. VERIFICATION ENGINEER, ASIC, VERILOG, SYSTEM VERILOG, SYSTEMVERILOG, RTL,... more

Sep 12 Verification Engineer (v.c) Genesisngn Chandler, AZ

Verification Methodology - OVM(Mandatory) System Verilog - SV(Mandatory) VLSI HVL Verification As a Lead, you are responsible for managing a small team of analysts, developers,... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and UVM. Support of full-chip verification, including digital circuits. This position requires a Bachelors degree in... more

Sep 11 Junior FPGA Engineer Ginas Tech Jobs Chicago, IL

infrastructure development -Developing unit/system test benches -Test automation ... -Understanding of hardware architecture -Verilog (SystemVerilog is a plus) -Experience... more

Sep 11 R&D Engineer, Staff Synopsys California

experience. · Exposure to Verilog/VHDL. · Exposure to System Verilog, UVM, VMM or OVM · Knowledge of IC Design flows. · Unix, Perl and Tcl Scripting Knowledge. · Knowledge of... more

Sep 11 Verification Engineer Enterprise Solutions Chandler, AZ

Verification Methodology - OVM(Mandatory) System Verilog - SV(Mandatory) VLSI HVL Verification As a Lead, you are responsible for managing a small team of analysts, developers,... more

Sep 11 FPGA Engineer Job Leidos Columbia, MD

• 2 years of experiences with Verilog (Systemverilog for verification) hardware ... language (including Systemverilog with OVM/UVM) Leidos Overview:Leidos is an applied... more

Sep 11 Principal/Sr. Principal DDR Verification Engineer Applied Micro Circuits Sunnyvale, CA

verification environment development using System Verilog based methodologies (OVM/UVM) ... * Experience using the HDLs (Verilog, System Verilog) * Experience using HVL like OVM,... more

Sep 10 FPGA Engineer Keyw Maryland

synthetic aperture radar image compression system. We are looking for an experienced ... image processing. Proficiency in System Verilog coding. Location: Severn, MD Degree:... more

Sep 10 Programmable Logic Engineer Viasat Atlanta, GA

methods using Verilog, and/or System Verilog hardware description language * ... including Verilog and/or System Verilog hardware description languages. Your... more

Sep 10 Junior FPGA Engineer Next Step Systems Naperville, IL

infrastructure development -Developing unit/system test benches -Test automation ... -Understanding of hardware architecture -Verilog (SystemVerilog is a plus) -Experience... more

Sep 10 Design Verification Engineer (NCG) Altera San Jose, CA

top and IP level design/verification using SystemVerilog/UVM. You are expected to ... in programmable logic solutions, enabling system designers and semiconductor companies to... more

Sep 10 ASIC VERIFICATION ENGINEER NVIDIA Santa Clara, CA

and system level verification - Expertise in System Verilog or similar HVL - Good debugging and problem solving skills - Perl and C/C++ programming language experience desirable -... more

Sep 09 C++ and System Verilog/UVM Engineer Hire IT People Marlborough, MA

Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. more

Sep 09 Digital Design and Verification Engineer Linear Technology Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 09 Verification Engineer S & A Associates Santa Clara, CA

with verification experience using system verilog and OVM. If you are available for verification work we have a number of openings to ... verification ovm system verilog... more

Sep 09 Verification Engineer Compnova.com Santa Clara, CA

programming ability in C, C++, System C and System Verilog Knowledge in CPU verification (Cache, Pipeline, Interrupt, ISG Concepts) Must be a highly organized, detail-oriented... more

Sep 07 FPGA ENGINEER Judge Group Atlanta, GA

of FPGA code including Verilog and/or System Verilog hardware description ... methods using Verilog, and/or System Verilog hardware description language... more

Sep 07 Electrical Engineer Sr Lockheed Martin Orlando, FL

Built-In-Test (BIT) and support of debug and system integration activities. Individual ... Experience with Verilog, C/C++, MathLab/Simulink, System Verilog languages; Synopsis Synpl... more

Sep 06 Digital Design Engineer Nxp Semiconductors Tempe, AZ

will be required using verilog and system verilog. Your Profile: This position requires excellent communication and problem solving skills. At least 5 years of digital design... more

Sep 05 Verification Engineer Ee-recruiters Santa Clara, CA

If you have current experience with SystemVerilog, OVM, UVM, or VMM ... are a Verification Engineer that has strong SystemVerilog and either UVM/OVM/VMM... more

Sep 05 Core/IP Verification Engineer for high-speed SerDes Encore Semi Raleigh, NC

and modeling in Verilog, VHDL, SystemVerilog, OVM/UVM Verification, Perl, TCL, ... • Expertise in implementing random constrained OVM/UVM system Verilog test benches and cov... more

Sep 05 Verification Engineer E-solutions Chandler, AZ

Verification Methodology - OVM(Mandatory) System Verilog - SV(Mandatory) VLSI HVL Verification * As a Lead, you are responsible for managing a small team of analysts, developers,... more

Sep 05 Verification Engineer Mastech Chandler, AZ

Methodology - OVM (Mandatory) System Verilog - SV (Mandatory) VLSI HVL Verification. Education: Bachelor's degree Experience: Minimum 5 years Relocation: No, this position will... more

Sep 04 Jr. Hardware Engineer Eagle Technical Staffing Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit / system testbenches Tes ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Sep 03 Staff Digital Design Engineer Silicon Laboratories Austin, TX

Skills, and Abilities: Verilog and SystemVerilog RTL and behavioral modeling ... languages, and a revision control system. Familiarity with system-on-chip... more

Sep 03 ASIC Verification Engineer - Boise, Idaho Job Micron Longmont, CO

ASIC verification, working closely with the system group, architects, design and ... developing Re-Usable Test Benches in SystemVerilog - Additional Skills: -... more

Sep 03 ASIC Design Engineer Footbridge - IT Division Westford, MA

plans, specifications and designs of UVM / System Verilog Based test benches. You will ... bench, drivers, monitors, scoreboards in System Verilog Create the test suites,... more

Sep 02 Senior Pre-Silicon Validation Engineer Intel Thousand Oaks, CA

not limited to: * Designing and debugging SystemVerilog-based verification testbenches ... is highly desired * Proficient in Verilog / System Verilog * Deep experience in... more

Aug 31 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Broadcom Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* Business Unit Broadband ... RTL design experience (VHDL/Verilog/SystemVerilog) and/or very strong OO... more

Aug 29 RTL/FPGA Design II (3401) Randstad Technologies - New Austin, TX

Verilog 2 ... static timing analysis. 5+ years of RTL, - Verilog, System Verilog, - VHDL experience 5+ years of FPGA design experience, preferably Xilinx FPGAs C omfortable... more

Aug 28 Digital Design Engineer Computer Express Tempe, AZ

is Mandatory Must have expert knowledge of Verilog Implementing test modes communicate ... 5 yrs of experience Knowledge of System Verilog Cadence NcSim Designing and... more

Aug 28 Sr. ASIC Design Verification Engineer Real Staffing Milpitas, CA

using higher level language like system verilog/specman-e etc. Must be able to create testplans describing coverage points. Expertise in creating random and directed tests to... more

Aug 28 Senior Design Verification Engineer Analog Devices Norwood, MA

level verification; programming using SystemVerilog or similar hardware verification ... and, using the Linux operating system. For positions requiring access to technical... more

Aug 27 System Verilog OVM UVM Systems Pros Minneapolis, MN

system verilog OVM UVM RTL Embedded processor subsystems memory bus controller Vinnie Majeski Systems Pros Inc 76 Treble Cove Road Bldg 2 Billerica MA 01862 Phone 800 891-2255 ext... more

Aug 26 Verification Engineer IV Cinder Solutions Santa Clara, CA

strong software skills with experience using System Verilog/Verilog, OVM/UVM. - Knowledge of Perl is preferred. - Candidates should also have experience with RTL simulators, VCS... more

Aug 22 Sr Electrical Engineer - ASIC/FPGA Rockwell Collins Cedar Rapids, IA

RTL blocks using VHDL or System Verilog. Applicants must be capable of obtaining a US ... coverage, SystemVerilog. • ASIC / FPGA lab validation with advanced lab... more

Aug 21 SoC Verification Eng Calsoftlabs-an Alten Group Company Raleigh, NC

if you do not have experience in System Verilog and either UVM (preferred) or OVM. 3+ ... verification effort of a complex chip, sub-system and/or blocks. You will define chip... more

Aug 21 ASIC Engineer 3 Juniper Networks Westford, MA

plans, specifications and designs of UVM / System Verilog Based test benches. You will use ... drivers, monitors, scoreboards in System Verilog * Create the test suites,... more

Aug 20 Multimedia Verification Engineers Collabera- Niche San Diego, CA

Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C. Experience with methodologies like ... Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting... more

Aug 20 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit / system testbenches Tes ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Aug 14 ASIC Developer Braves Technologies Irvine, CA

tes who are CAP Exempt and have a valid stamped H1B visa shouldapply.Location: Irvine CA. ASIC DeveloperSkills Required: ASIC Must have experience in System Verilog/ Verilog,OVM,... more

Aug 14 Engineer, Digital IC Design Marvell Technology Group Santa Clara, CA

to tape-out . Familiar with ARM SOC embeded system and AMBA. . Understanding of DDR, ... and NVMe would be a plus. . Understanding of System Verilog would be a plus . more

Aug 11 SoC Verification Engineer : C/C++, TCP, DMA, DDR, AMBA Xpeerant Raleigh, NC

of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++ - Must have hands-on ... -Extensive UVM/System verilog skills, as well as exposure to DDR, I2C, AMBA, and PCIe test... more

Aug 11 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

hardware description languages such as VHDL, Verilog, or SystemVerilog. This ... design opportunities include:• Digital system design using FPGAs and software defined... more

Aug 06 FPGA VERIFICATION ENGINEER - SWITCHING DIVISION (3 Georgia Department of Labor Alpharetta, GA

verification languages is required. SystemVerilog experience is preferred. ... oriented hardware verification languages, SystemVerilog is preferred. Knowledge and... more

Aug 05 FPGA Verification Engineer Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Aug 05 VLSI Verification - System Verilog Mindlance Raleigh, NC

order - 252640 Title - VLSI Verification - System Verilog Location - Raleigh ,NC ... Skills/Experience: Must have experience in System Verilog and either UVM (preferred) or OV... more

Aug 05 Senior Member Technical Staff Mentor Graphics Incorporation Indiana

verification • Required: Strong Verilog/System Verilog Experience, Strong C++ PLI experience, Good Assembly understanding, Some bus protocol understanding ( e.g. PCI, AXI ) •... more

Aug 02 Design Verification Engineer - Interconnect Middlesex Community College Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jul 29 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of... more

Jul 25 Design Verification Engineer Cirrus Logic Austin, TX

HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/OVM, UVM, AVM, Vera, e) required. ... and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS. more

Jul 24 Hardware Verification Engineer (MemC/DDR PHY experience) (E1924523) QUALCOMM Raleigh, NC

experience *LI-SRC Keywords System Verilog, UVM, Verification, IP Verification, DDR, Memory Controller You will need to login into your profile to apply for this job. If you... more

Jul 15 Design Verification Engineer - Interconnect Artisan Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jul 10 Senior ASIC Design Engineer ( Frontend ) Radiant Systems San Diego, CA

data formats including timing, power, area, system performance, SDC, VCD, FSDB, SAIF, ... used hardware description languages such as Verilog, VHDL and System Verilog Strong... more

Jul 08 Senior Staff Digital Design Engineer Atmel San Jose, CA

and mixed-signal simulators * Knowledge of Verilog and/or System Verilog language for ... Skills * Knowledge and ability to use System Verilog Assertions * Knowledge and... more

Jul 07 ASIC Architect - Technologist Hitachi Global Storage Technologies San Jose, CA

other engineering departments including system architecture, hardware, and software ... and results Experience with Verilog/System Verilog, C/C++, linux, scripting... more

Jul 04 Member Consulting Staff Mentor Graphics Indiana

Optimization, code coverage and system Verilog language support Good Understanding ... structure, algorithm and familiarity with system Verilog/VHDL/TCL/TK Candidate should... more

Jul 01 IC Design Verficiation Engineer Avago Technologies Allentown, PA

processor products. The candidate will use SystemVerilog, Verilog and other Unix ... using behavioral simulation using System Verilog, VMM or UVM methodologies. *... more

Jun 30 Digital Design Engineer Inphi Thousand Oaks, CA

implementing RTL designs using Verilog/SystemVerilog; implementing verification test ... of digital and mixed-signal circuits; Verilog or System Verilog to verify functional... more

Jun 30 MTS ASIC Verification Design Engineer Cameron Resources Group Massachusetts

test libraries, software modeling, Verilog modeling, test development, ... caches Must be proficient in Verilog, System Verilog, C and C++, OVM/ UVM, Perl, Unix... more

Jun 27 RTL Designer Spectraforce Technologies East Brunswick, NJ

development using Verilog and SystemVerilog Creating test benches and ... simulations for functional validation using Verilog and System Verilog Working knowledge... more

Jun 20 Design Verification Engineer 2 AMD Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 20 Pre-Silicon Functional Validation Hillsboro, OR

members with methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to backbone (IOSF). PCIE background is a bonus which will help... more

Jun 17 FPGA Engineer III - Bothell Sonosite Washington

(VHDL, System Verilog, System C or C/C , scripting in Bash, Python, Perl, or Tcl). ��� Experience with ISO, FDA, or other regulated product development environments is a plus. ���... more

Jun 10 Digital Design Engineers (AMRD356-357) Fortinet Sunnyvale, CA

Verilog and System Verilog syntax constructs • Experience with DDR3/QDR/XAUI. • ... understanding of simulation and synthesis implications of various Verilog RTL... more

Jun 09 Sr Staff Engineer Seagate Minnesota

utilizing Unix, Linux, Synopsys Tools, and Verilog. Experience running large scale ... Experience designing in Verilog and/or System Verilog... more

Jun 06 Memory Subsystem Design Engineer Talarience Folsom, CA

and/or software architects to develop system models, evaluate memory system ... models and evaluation tools in C/C++, system Verilog and similar environments. more

Jun 05 Engineer Circuit Design 4 Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. EGPD2014Basic... more

May 31 Engineer, ASIC Design Verification Results Center Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 30 Engineer, ASIC Design Verification Marvell Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 20 IC Verification Engineer eTech Hi Simi Valley, CA

candidate will have experience using System Verilog, Specman e, Vera or System C) ... * Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.If interested... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired ... a plus. Knowledge of ARM microprocessor-system is a big plus. Very strong... more

Apr 28 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

implementing, debugging, and closing SystemVerilog functional coverage groups. ... experience Candidate SHOULD also have system verilog test bench experience. We need... more

Apr 25 Co-Op Engineer Amd | Seamicro Austin, TX

- Understanding and some experience with Verilog, C/C++, Perl, and logic simulation is a r ... - Experience with SystemVerilog/OVM is a plus... more

Mar 25 Analog Behavioral Modeling Engineer Recruiting Engine (mls) San Diego, CA

testing. Experience with Modelsim, NC-Verilog, VCS or similar digital logic ... Experience with Verilog and/or System Verilog Experience with Cadence-AMS or similar AMS m... more

Mar 24 Digital Design Engineer Google Mountain View, CA

the lowest levels of circuit design to large system design and see those systems all the ... Proficient in RTL / Logic / Verilog / System Verilog. * Successfully delivered... more

Mar 24 Senior Digital Design Engineer On Semiconductor Ireland, IN

in front-end design tools * Knowledge of systemVerilog is desirable. * Self driven individual and a good team player. * Diligent, detail-oriented, and willing to take initiative... more

Mar 12 ASIC Verification Engineer Systel Santa Clara, CA

like VMM, OVM, UVM Development will be done System Verilog Develop test plans, execute ... environment using Constraint Random, SystemVerilog Assertions Strong knowledge of... more

Mar 12 Senior Verification Engineer Aba Search San Jose, CA

o Hardware modeling using UVM, Verilog, System Verilog or C/C++ o 6 + years of ... functional coverage o Expertise in System Verilog, OVM/UVM or Vera based tools o... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

SICs Knowledge of video codec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC,... more

Mar 04 Verification Group Manager Direct Staffing Austin, TX

products. Strong background with HDLs (e.g. Verilog, VHDL), HVLs (e.g. SystemVerilog/OVM, ... models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing... more

Feb 13 Principal Verification Engineer Aba Search San Jose, CA

and development and modeling using UVM, SystemVerilog, Verilog. EXPERIENCE o ... verification languages OVM/UVM/System Verilog/C++ o Expertise in putting... more

Feb 12 Design Verification Engineer Commnexus Santa Clara, CA

programming ability in C, C++, System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Feb 06 Senior Staff Design Engineer Xilinx San Jose, CA

· Expert level understanding of Verilog, SystemVerilog, Timing Constraints and Digital Design principles. · Hands on experience of Front End Design and Implementation steps... more

Jan 08 Sr. R&D Engineer Real Intent California

of the following fields: GUI, Verilog/System Verilog/VHDL Compilation, Synthesis ... and verification flow, working knowledge of Verilog, VHDL, and SystemVerilog... more

Dec 31 FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL Darwin Recruitment Newport Beach, CA

FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL FPGA/ASIC Designer - Darwin Recruitme ... or equivalent academic qualification. System Verilog or Specman Cadence E... more

Dec 02 Verification Engineer Cypress Semiconductor Colorado Springs, CO

Skills Digital Verification using System Verilog Experience using OVM or UVM, ... Experience Digital Verification using System Verilog Experience using OVM or UVM,... more

Jun 05 Engineer, ASIC Design Verification Marvell Technology Group Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

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