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Jul 23 SoC Verification Eng--North Carolina---Immediate Interviews Calsoftlabs-an Alten Group Company Raleigh, NC

if you do not have experience in System Verilog and either UVM (preferred) or OVM. 3+ ... verification effort of a complex chip, sub-system and/or blocks. You will define chip... more

Jul 23 VHSIC Hardware Description Language ( VHDL ) Developer Univercity Staffing's Client Boston, MA

designs operating within an integrated system Desired Qualifications: The optimal ... OpenVPX, Verilog, Matlab, Perl, and/or system Verilog Education and Experience... more

Jul 23 44308-Design Automation Engineer Entegee New Brighton, MN

Linux operating system on host nodes • Setup job scheduling for these resources • ... Cadence – Incisive, VCS) • Deep knowledge of Verilog, System Verilog languages • Working k... more

Jul 23 IC Design Verficiation Engineer Avago Technologies Allentown, PA

products.��� The candidate will use SystemVerilog, Verilog and other Unix scripting ... using System Verilog, VMM or UVM methodologies. * Candidate must have strong... more

Jul 23 Design Verification Engineer Altera San Jose, CA

and/or verification experience. Fluent in SystemVerilog. Familiar with OVM/VMM/UVM ... in verilog RTL design, verification, VCS Verilog simulator, Leda Lint tool and... more

Jul 22 Pre-Silicon Validation Engineer Intel California

not limited to: * Designing and debugging SystemVerilog-based verification testbenches ... validation experience * Proficient in Verilog / System Verilog * Proficient in OVM... more

Jul 22 ASIC Engineer Aerotek Denver, CO

Engineers is preferred. - Exposure to System Verilog and experience with Xilinx ... Skills for ASIC Engineer Job: * ASIC RTL * VERILOG / VHDL * SYSTEMVERILOG * BSEE *... more

Jul 22 Design Verification Engineer Huntech Consultants San Diego, CA

experience. Experience with one or more of: System Verilog, SVA, Vera . Experience with ... one or more of: OVM, VMM, RVM. Familiar with Verilog or VHDL. Scripting and automation... more

Jul 22 Mixed-signal Functional verification Intel California

creation using VHDL and knowledge of Verilog/System Verilog is beneficial - ... different model language(Verilog/VHDL, systemverilog would be nice to have) ���... more

Jul 22 ASIC Verification Consultant Einfochips San Jose, CA

Strong programming skills using C++ and Verilog. Experience with writing a detailed ... and memory interfaces. Experience with System Verilog is strongly desired. more

Jul 22 Design Methodology Engineeer Systems Security Services Austin, TX

coding in HDL languages such as Verilog, SystemVerilog or VHDL Experience with ... methodologies including UVM/OVM, SystemVerilog, functional coverage and... more

Jul 22 Sr Design Engineering Manager, Functional Verification, DDR Design Team Classifiedads.com San Jose, CA

as applies to DDR Design IP, using a System Verilog-based coverage-driven ... with coverage-driven verification with SystemVerilog or Specman ‘e’ * Experience... more

Jul 21 Principal/Sr. Principal RTL Verification Engineer (Processor) Applied Micro Circuits Sunnyvale, CA

environment development using System Verilog based methodologies (OVM/UVM) * ... assembly tests * Experience using the HDLs (Verilog, System Verilog) * Experience using... more

Jul 21 Senior Staff Verification Engineer (UVM) Kforce Inc. San Jose, CA

Verilog AMS is a plus Very strong System Verilog programming skills. Solid ... Perl or Tcl Must have experience building SystemVerilog test-benches from scratch... more

Jul 21 FPGA Engineer Request Technology-anthony Honquest Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit/system testbenches Test ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Jul 21 Jr. FPGA Engineer Chicago Financial Search Chicago, IL

infrastructure development Developing unit / system testbenches Test automation ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Jul 20 Power Electronics Design Engineer Newtown Solutions Fargo, ND

Verilog and System Verilog (Verilog Preferred) • Test Bench Design and simulation methodology. (Xilinx and Modelsim tools preferred). • DDR, DDRII, DDRIII, mDDR, mDDRII, NAND... more

Jul 20 Pre-Silicon Functional Validation Synergy Seven Hillsboro, OR

members w/ methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to (IOSF). PCIE background is a bonus which will help in... more

Jul 20 Sr Electrical Engineer-ASIC/FPGA Rockwell Collins Cedar Rapids, IA

of RTL blocks using VHDL or System Verilog. • Proficiency using ASIC and/or FPGA ... functional coverage, SystemVerilog) • ASIC / FPGA lab validation with advanced lab... more

Jul 18 FGPA Development Engineer Sublime Wireless Raleigh, NC

Verilog, VHDL, Spec man, and / or System Verilog. System Verilog / UVM preferred. Experience with verification of complex state functions requiring significant wall time to... more

Jul 18 Design Automation Engineer Inginaire Mounds View, MN

Incisive, VCS) Deep knowledge of Verilog, System Verilog languages Working knowledge of ... Working knowledge of/with Specman e, System C languages is preferred Working... more

Jul 17 Verification/Design Intern On Semiconductor Plano, TX

and system level test •Automation of SIP development flow and view ... Verilog, System Verilog •Scripting Languages: C, Perl •Must have demonstrable problem... more

Jul 17 Principal Verification Engineer Hitachi Global Storage Technologies San Diego, CA

system level verification. * Competent in system Verilog, UVM verification flows * ... elements * Logic design experience in Verilog/VHDL Added Skill... more

Jul 17 Digital Verification Engineer(s) for Mixed-Signal Products - Californ Calsoft Labs San Diego, CA

2. Working knowledge of Object-Oriented SystemVerilog principles including experience ... System... more

Jul 16 Mixed-signal Functional verification Job Intel Santa Clara, CA

creation using VHDL and knowledge of Verilog/System Verilog is beneficial - ... Basic knowledge of different model language(Verilog/VHDL, systemverilog would be nice to... more

Jul 16 CAD Engineer, Front-End Methodology Apple Austin, TX

products. * Expertise in Verilog and System Verilog is required. * Expertise in TCL and ... comfortable with co-developing an existing system. * Description: You will be... more

Jul 14 Design Methodology Engineer KP Recruiting Group Austin, TX

coding in HDL languages such as Verilog, SystemVerilog or VHDL??? Experience with ... methodologies including UVM/OVM, SystemVerilog, functional coverage and... more

Jul 14 Logic Design Engineer Marvell Technology Group Santa Clara, CA

of CPU architecture; understanding of Verilog, simulator, debug •Experience with ... code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is a... more

Jul 14 WLAN Verification Engineer Radiant System Massachusetts

testbench and reference model code in SystemVerilog C and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Jul 13 Engineer Asic Ericsson San Jose, CA

benches for the network processor blocks in system Verilog, C/C++, DPIs. To apply, email resume to Eus. Job search.T@ericsson .com and MUST reference Job ID# 14-CA-EAS4-2344. more

Jul 13 FPGA Engineer Job Leidos Columbia, MD

• 2 years of experiences with Verilog (Systemverilog for verification) hardware ... language (including Systemverilog with OVM/UVM) Leidos Overview:Leidos is an applied... more

Jul 12 Power Management Design Verification and Methodology Engineer Encore Semi Folsom, CA

and low-power design verification using SystemVerilog, OVM and UPF, in particular: - Client side power management - ACPI states (c-states/s-states) - Boot flows • The candidate... more

Jul 11 Asic Engineer Eagle Technical Staffing Denver, CO

in RTL source code development with Verilog or VHDL is a must. Expertise with ... Engineers is preferred. Exposure to System Verilog and experience with Xilinx... more

Jul 11 Junior FPGA Engineer (MS071031) Parallel Partners Chicago, IL

infrastructure development -Developing unit/system test benches -Test automation ... -Understanding of hardware architecture -Verilog (SystemVerilog is a plus) -Experience... more

Jul 11 Software Developer III Cinder Solutions Hillsboro, OR

plans, test benches and functional tests in system Verilog. - Prepare specifications, ... Experience with Verilog, System Verilog, System C, using OVM/UVM methods. -... more

Jul 10 ASIC Design Engineer Staff Juniper Networks Sunnyvale, CA

networking ASICs. Implement the design in Verilog Synthesize the design using Synopsys ... of industry experience • Strong Verilog, or SystemVerilog skills • Strong SystemC or... more

Jul 10 Senior ASIC Design Engineer ( Frontend ) Radiant Systems San Diego, CA

data formats including timing, power, area, system performance, SDC, VCD, FSDB, SAIF, ... used hardware description languages such as Verilog, VHDL and System Verilog Strong... more

Jul 08 Principal Verification IC Design Engineer Broadcom San Jose, CA

level. • Experience using SystemVerilog, VMM or UVM. • Familiar with System Verilog Assertions. • Strong experience in ASIC design verification flows and DV methodologies. •... more

Jul 08 ASIC DV Contractor (San Jose) Technical Link San Jose, CA

ASIC design flows Working experience with SystemVerilog andor UVM Knowledge of wireless ... and good grasp of DSP fundamentals is desirable. ASIC Design, RTL, System Verilog DSP... more

Jul 08 Senior Design Verification Engineer (EK) A Cirrus Logic Austin, TX

models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing ... analog and mixed signal IC's?Verilog or System Verilog experience?The ideal candidate... more

Jul 07 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

Responsibilities:FPGA infrastructure developmentDeveloping unit / system testbenchesTest a ... of hardware architectureVerilog (SystemVerilog is a plus)Experience of full... more

Jul 06 Digital Design Verification Engineer Collabera- Niche Massachusetts

digital ASIC verification tests in SystemVerilog and other verification ... testbench and reference model code in SystemVerilog, C, and Matlab in a UVM... more

Jul 04 Member Consulting Staff Mentor Graphics Indiana

Optimization, code coverage and system Verilog language support Good Understanding ... structure, algorithm and familiarity with system Verilog/VHDL/TCL/TK Candidate should... more

Jul 04 Member Consulting Staff Mentor Graphics Incorporation Indiana

Optimization, code coverage and system Verilog language support Good Understanding ... structure, algorithm and familiarity with system Verilog/VHDL/TCL/TK Candidate should... more

Jul 03 FPGA VERIFICATION ENGINEER - SWITCHING DIVISION Georgia Department of Labor Alpharetta, GA

verification languages is required. SystemVerilog experience is preferred. ... oriented hardware verification languages, SystemVerilog is preferred. Knowledge and... more

Jul 02 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Broadcom Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* Business Unit Mobile ... RTL design experience (VHDL/Verilog/SystemVerilog) and/or very strong OO... more

Jun 30 MTS ASIC Verification Design Engineer Cameron Resources Group Massachusetts

test libraries, software modeling, Verilog modeling, test development, ... caches Must be proficient in Verilog, System Verilog, C and C++, OVM/ UVM, Perl, Unix... more

Jun 30 Digital Design Engineer Inphi Thousand Oaks, CA

implementing RTL designs using Verilog/SystemVerilog; implementing verification test ... of digital and mixed-signal circuits; Verilog or System Verilog to verify functional... more

Jun 28 CPU Sub-System Verification Engineer Randstad Technologies - New Cary, NC

/ write test code using ARM assembly and System Verilog - Run simulation and coverage ... entry, simulation, and debug tools - System Verilog experience, including use of UVM/OVM... more

Jun 27 RTL Designer Spectraforce Technologies East Brunswick, NJ

development using Verilog and SystemVerilog Creating test benches and ... simulations for functional validation using Verilog and System Verilog Working knowledge... more

Jun 27 Verification Engineer II Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog. Support of full-chip verification. This position requires a Bachelor degree with minimum of 2 years of related... more

Jun 26 Design Verification Lead Commnexus Santa Clara, CA

programming ability in C, C , System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Jun 25 Software Developer - 7640 eTech Resources Hillsboro, OR

test benches and functional tests in system Verilog. Prepare specifications, evaluates ... - Experience with Verilog, System Verilog, System C, using OVM/UVM... more

Jun 23 Design Verification Engineer - Interconnect Artisan Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jun 23 Design Verification Engineer - Interconnect Middlesex Community College Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jun 23 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of... more

Jun 20 Contract - Front End RTL development and Verification Xilinx San Jose, CA

and background in RTL-based (Verilog and System Verilog) high speed digital design · Familiar with verification methodologies and able to debug RTL issues. ·... more

Jun 20 Pre-Silicon Functional Validation Hillsboro, OR

members with methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to backbone (IOSF). PCIE background is a bonus which will help... more

Jun 20 Electrical Engineer Sr Lockheed Martin Orlando, FL

skills. Familiarity with video system design, synchronization, image ... with Verilog, C/C++, MathLab/Simulink, System Verilog languages; Synopsis Synplify,... more

Jun 20 Design Verification Engineer 2 AMD Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 17 FPGA Engineer III - Bothell Sonosite Washington

(VHDL, System Verilog, System C or C/C , scripting in Bash, Python, Perl, or Tcl). ��� Experience with ISO, FDA, or other regulated product development environments is a plus. ���... more

Jun 16 Design Verification Engineers Collabera San Diego, CA

verification languages (OO HVLs) like SystemVerilog, Vera, Specman or SystemC. A ... for calling C++ and systemC functions from System Verilog UVM test bench. Create... more

Jun 16 Elect Design Engineer Staff Cypress Semiconductor Colorado Springs, CO

flows. Desired knowledge includes C, C++, System C, System Verilog, Makefiles, C-shell scripts, Perl, Unix / Linux, MS office products (Word, Excel, PowerPoint, Project). The... more

Jun 14 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

hardware description languages such as VHDL, Verilog, or SystemVerilog. This ... design opportunities include:• Digital system design using FPGAs and software defined... more

Jun 11 Digital Design Engineers (AMRD356-357) Fortinet Technologies Sunnyvale, CA

Verilog and System Verilog syntax constructs •Experience with DDR3/QDR/XAUI. ... of various Verilog RTL constructs Educational Requirement: •Masters degree in Electrical... more

Jun 10 Digital Design Engineers (AMRD356-357) Fortinet Sunnyvale, CA

Verilog and System Verilog syntax constructs • Experience with DDR3/QDR/XAUI. • ... understanding of simulation and synthesis implications of various Verilog RTL... more

Jun 10 Design Engineer Teledyne Technologies Buellton, CA

Built-In-Test (BIT) and support of debug and system integration activities. Individual ... Experience with Verilog, C/C , MatLab/Simulink, System Verilog languages; Synopsis Symplif... more

Jun 09 Sr Staff Engineer Seagate Shakopee, MN

utilizing Unix, Linux, Synopsys Tools, and Verilog. Experience running large scale ... Experience designing in Verilog and/or System Verilog... more

Jun 09 Design Engineer Teledyne Cable Solutions Buellton, CA

Built-In-Test (BIT) and support of debug and system integration activities. Individual ... Experience with Verilog, C/C , MatLab/Simulink, System Verilog languages; Synopsis Symplif... more

Jun 09 SoC Verification Engineer : C/C++, TCP, DMA, DDR, AMBA Xpeerant Raleigh, NC

of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++ - Must have hands-on ... with TCP offload and DMA.-Extensive UVM/System verilog skills, as well as exposure to... more

Jun 06 Memory Subsystem Design Engineer Talarience Folsom, CA

and/or software architects to develop system models, evaluate memory system ... models and evaluation tools in C/C++, system Verilog and similar environments. more

Jun 04 Programmable Logic Engineer 85 Cor-tech Atlanta, GA

code including Verilog and/or System Verilog hardware description languages. Your ... methods using Verilog, and/or *System Verilog hardware description... more

May 31 Engineer, ASIC Design Verification Results Center Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 30 Engineer, ASIC Design Verification Marvell Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 20 IC Verification Engineer eTech Hi Simi Valley, CA

candidate will have experience using System Verilog, Specman e, Vera or System C) ... * Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.If interested... more

May 16 Engineer Circuit Design- 4 Abacus Service Redondo Beach, CA

with an emphasis on expertise in System Verilog and OVM/UVM methodology? MUST ... with an emphasis on expertise in System Verilog and OVM/UVM methodology. more

May 15 Engineer Circuit Design- 4 (5) Chipton Ross California

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... with an emphasis on expertise in System Verilog and OVM/UVM... more

May 14 Analog/Mixed Signal Functional Verification Engineer (Temp Position) (E1916549) QUALCOMM San Diego, CA

or equivalent experience Keywords SystemVerilog UVM Verilogams SVA Verilog You will need to login into your profile to apply for this job. If you are a new user, click here... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

C/C , VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired ... plus. Knowledge of ARM microprocessor-system is a big plus. Very strong debug/analytical... more

Apr 28 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage ... experience Candidate SHOULD also have system verilog test bench experience. We need... more

Apr 23 Principal Application Engineer Cadence Design Systems San Jose, CA

e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience ... SystemVerilog, Specman e, VHDL, verilog Methodologies: Preferable experience in... more

Apr 09 SENIOR ASIC VERIFICATION ENGINEER NVIDIA Westford, MA

and system level verification - Expertise in System Verilog or similar HVL - Good debugging and problem solving skills - Perl and C/C++ programming language experience - Good... more

Apr 07 Staff Application Engineer Cadence Design Systems Austin, TX

e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience ... SystemVerilog, Specman e, VHDL, verilog Methodologies: Preferable experience in... more

Mar 25 Analog Behavioral Modeling Engineer Recruiting Engine (mls) San Diego, CA

testing. Experience with Modelsim, NC-Verilog, VCS or similar digital logic ... Experience with Verilog and/or System Verilog Experience with Cadence-AMS or similar AMS m... more

Mar 24 Digital Design Engineer Google Mountain View, CA

the lowest levels of circuit design to large system design and see those systems all the ... Proficient in RTL / Logic / Verilog / System Verilog. * Successfully delivered... more

Mar 14 Sr. Design Verification Engineer - Mixed Signal Alliance Solutions Austin, TX

•Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/OVM, UVM, ... in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing and Verilog... more

Mar 13 ASIC Verification Engineer Embedded Resource Group Mountain View, CA

knowledge of System Verilog + UVM bull System level validation requiring knowledge of C coding bull PERLUnix scripting Desired bull Debug ability using Verdi waveform debugger is... more

Mar 04 Verification Group Manager Direct Staffing Austin, TX

products. Strong background with HDLs (e.g. Verilog, VHDL), HVLs (e.g. SystemVerilog/OVM, ... models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing... more

Feb 20 Applications Engineer - Verification Tabula Santa Clara, CA

Skills: 3+ years of industry experience Verilog/SystemVerilog coding experience UVM/OVM Assertion-based verification Creation of verification environments that implement... more

Feb 13 Principal Verification Engineer Aba Search San Jose, CA

and development and modeling using UVM, SystemVerilog, Verilog. EXPERIENCE o ... verification languages OVM/UVM/System Verilog/C++ o Expertise in putting... more

Feb 07 Programmable Logic Engineer Viasat Atlanta, GA

methods using Verilog, and/or System Verilog hardware description language * ... including Verilog and/or System Verilog hardware description languages. Your... more

Jan 28 Senior Verification Engineer HP Fort Collins, CO

At Hewlett-Packard, we invent new technologies, change markets, and create business opportunities. Teamwork, initiative, innovation, and appropriate ... 10 years of industry... more

Jan 11 Systems Design Engineer (FPGA) Job Micron Folsom, CA

but not be limited to: - FPGA design in SystemVerilog/Verilog - Firmware development in C/C++ - PCB design - Debugging of FPGA and SoC based, high-speed memory systems -... more

Jan 08 Sr. R&D Engineer Real Intent California

of the following fields: GUI, Verilog/System Verilog/VHDL Compilation, Synthesis ... and verification flow, working knowledge of Verilog, VHDL, and SystemVerilog... more

Jan 07 ASIC Verification Engineer Systel Santa Clara, CA

like VMM, OVM, UVM Development will be done System Verilog Develop test plans, execute ... environment using Constraint Random, SystemVerilog Assertions Strong knowledge of... more

Jan 07 Senior Verification Engineer Aba Search San Jose, CA

o Hardware modeling using UVM, Verilog, System Verilog or C/C++ o 6 + years of ... functional coverage o Expertise in System Verilog, OVM/UVM or Vera based tools o... more

Dec 31 FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL Darwin Recruitment Newport Beach, CA

FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL FPGA/ASIC Designer - Darwin Recruitme ... or equivalent academic qualification. System Verilog or Specman Cadence E... more

Oct 31 Intern (Technical) Synopsys California

Languages coding experience preferably in Verilog/Vera/System Verilog is preferable. The candidate must have completed Bachelors degree in electronics/ Electrical engg. Partial... more

Jun 05 Engineer, ASIC Design Verification Marvell Technology Group Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 31 C++ and System Verilog/UVM Engineer Hire IT People Marlborough, MA

Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. more

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