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Aug 22 FPGA, Verilog, Asic, SystemVerilog - Trading Firm - $200,000 Hunter Bond Chicago, IL

FPGA, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently seeking a ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Aug 21 Systemverilog / UVM Design Verification Consultant Intelliswift Software Mountain View, CA

candidate having more active experience with SystemVerilog coding. - Experience writing good SystemVerilogUVM testbench code UVM, PCIe, Design & Verification; SerDes / PCIe /... more

More Job Postings from the Web
Aug 22 Digital Design Verification Engineer Texas Instruments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Aug 22 Lead Design Verification Electrical Engineer Compound Photonics Vancouver, WA

the functional verification of ASICs using System Verilog and UVM methodologies. She/he ... ASIC verification infrastructure in System Verilog and pref Specman-e Hands-on... more

Aug 22 SOC Design Verification Engineer Classifiedads.com Santa Clara, CA

RTL, VHDL, Verilog, System Verilog, System Verilog Assertions (SVA), Vera, e-Specman, etc. -Knowledge of SOC, ARM processor, AMBA bus, DDR, or peripherals is preferred -Scripting... more

Aug 22 Digital Design Verification Engineer Texas Instrutments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Aug 22 Multimedia Verification Engineers Collabera- Niche San Diego, CA

of HVLs System Verilog VERA e Specman System C Experience with methodologies like ... tool like Veloce Palladium is a plus Verilog or VHDL C C Tcl Perl shell scripting... more

Aug 21 Digital Verification Engineer(s) for Mixed-Signal Products - Californ Calsoft Labs San Diego, CA

2. Working knowledge of Object-Oriented SystemVerilog principles including experience ... System... more

Aug 21 FPGA Engineer Request Technology-craig Johnson Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit/system testbenches Test ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Aug 21 Hardware/Verification Design Engineer Imagination Technologies Sunnyvale, CA

assembly programming, CC++, Verilog and SystemVerilog Strong coding and problem ... verification, validation, cache, coherence, processor, pipeline, UVM, System Verilog,... more

Aug 21 Staff ASIC Verification Engr Job SanDisk Salt Lake City, UT

Req ID: 21666 Developing module as well as system level verification test-bench ... and work experience with SystemVerilog constrained random testbench development,... more

Aug 21 ASIC Engineer 3 Juniper Networks Westford, MA

plans, specifications and designs of UVM / System Verilog Based test benches. You will use ... drivers, monitors, scoreboards in System Verilog * Create the test suites,... more

Aug 21 Senior Hardware Verification Engineer Amazon Cupertino, CA

* Write scripts to automate tests * Develop Verilog testbenches and tests for pre-silicon ... of SoCs * 5+ years of experience in Verilog HDL and SystemVerilog * 5+ years of... more

Aug 21 FPGA Prototyping Engineer, Platform Architecture Apple California

Logic Design and verification using Verilog and System Verilog. * Designing keeping in mind FPGA (Xilinx Virtex/Spartan Series or Altera Stratix/ Cyclone series) features and... more

Aug 21 Junior FPGA Engineer Request Technology-robyn Honquest Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit/system testbenches Test ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Aug 20 Principal/Sr. Principal DDR Verification Engineer Applied Micro Circuits Sunnyvale, CA

verification environment development using System Verilog based methodologies (OVM/UVM) ... * Experience using the HDLs (Verilog, System Verilog) * Experience using HVL like OVM,... more

Aug 20 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

Responsibilities: FPGA infrastructure development Developing unit / system testbenches Tes ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Aug 20 IC Design Verficiation Engineer Avago Technologies Allentown, PA

processor products. The candidate will use SystemVerilog, Verilog and other Unix ... using behavioral simulation using System Verilog, VMM or UVM methodologies. *... more

Aug 19 Senior Digital Verification Engineer Cyient San Jose, CA

understanding of Object Oriented System Verilog principles including OVM or UVM. ... OVM or UVM (or at least VMM), verification (systemverilog, ovm/uvm/vmm, random... more

Aug 19 Engineer, Design Verification Marvell Technology Group Santa Clara, CA

of CPU architecture; understanding of Verilog, simulator, debug • Experience with ... code coverage) • Familiarity with SystemVerilog/UVM/formal verification/emulation is a... more

Aug 19 FPGA Design Engineer Connected Systems Partners Stamford, CT

as well as Modelsim. Any experience with SystemVerilog, (UVM and/or OVM), C/C++ are also a plus Any experience working with telecom, control systems and networking companies is... more

Aug 19 Engineer Circuit Design- 4 (Job Nbr 14006467) PDS Tech Redondo Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... functional coverage using PSL or SVA, and modeling using C/C++, SystemVerilog, or... more

Aug 18 ASIC RTL Design Engineer Encore Semi San Diego, CA

ing synthesis, simulation, and timing tools. • Use of third party IP cores including microprocessors and peripheral cores. • VHDL experience required, SystemVerilog experience is... more

Aug 18 SoC Verification Engineer Altera Texas

to the following: Developing unit/core/system level testbench, BFMs (Bus Functional ... methodologies (such as UVM, OVM, System Verilog, constrained-random stimulus... more

Aug 18 CPU Verification Engineer Aerotek Cary, NC

-Buzzwords: validation, verification, SystemVerilog, OVM/UVM, test bench 3. ... programming skills (C++, System Verilog) If you're interested, please contact... more

Aug 18 Sr Design Verification Engineer International Recruit Group Austin, TX

mixed signal IC's? Do you have Verilog or System Verilog experience? If you answered ... models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing... more

Aug 17 Electrical Engineer Sr Lockheed Martin Orlando, FL

skills. Familiarity with video system design, synchronization, image ... with Verilog, C/C++, MathLab/Simulink, System Verilog languages; Synopsis Synplify,... more

Aug 17 Senior Firmware Engineer Confidential San Diego, CA

Verification Engineer (job code: 4HN0201): Develop UVM/System Verilog based test benches, add assertions and cover groups to collect code and functional coverage. Mail resume to... more

Aug 17 Power Electronics Design Engineer Newtown Solutions Fargo, ND

Verilog and System Verilog (Verilog Preferred) • Test Bench Design and simulation methodology. (Xilinx and Modelsim tools preferred). • DDR, DDRII, DDRIII, mDDR, mDDRII, NAND... more

Aug 15 ASIC Design Verification Engineer Real Staffing Santa Clara, CA

in lieu of BS + 5. May travel to client sites throughout U.S. Experience with Display Port, HDMI, Bluetooth, PERL, ASIC design & validation, Verilog, System Verilog-OVM... more

Aug 15 Design Verification Engineer Symphonyteleca Hudson, NH

Work with Verilog/System Verilog/ C Programming/scripting languages/ logic analyzers/ osci ... Microcontrollers Embedded Software Verilog System Verilog C Programming Scripting... more

Aug 15 FPGA, Verilog, Asic, SystemVerilog - Trading Firm - $200,000 Chicago, IL

a work visa considered Hunter Bond FPGA, Verilog, Asic, SystemVerilog Prestigious ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Aug 14 FPGA Engineer Veredus Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full ... infrastructure development Developing unit / system testbenches Test automation Follow us... more

Aug 14 ASIC Developer Braves Technologies Irvine, CA

tes who are CAP Exempt and have a valid stamped H1B visa shouldapply.Location: Irvine CA. ASIC DeveloperSkills Required: ASIC Must have experience in System Verilog/ Verilog,OVM,... more

Aug 12 Software Developer III Cinder Solutions Hillsboro, OR

plans, test benches and functional tests in system Verilog. - Prepare specifications, ... Experience with Verilog, System Verilog, System C, using OVM/UVM methods. -... more

Aug 12 FPGA Engineer Job Leidos Columbia, MD

• 2 years of experiences with Verilog (Systemverilog for verification) hardware ... language (including Systemverilog with OVM/UVM) Leidos Overview:Leidos is an applied... more

Aug 11 SoC Verification Engineer : C/C++, TCP, DMA, DDR, AMBA Xpeerant Raleigh, NC

of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++ - Must have hands-on ... -Extensive UVM/System verilog skills, as well as exposure to DDR, I2C, AMBA, and PCIe test... more

Aug 11 Embedded Systems Researcher Georgia Tech Research Institute/gtri Atlanta, GA

description language, such as Verilog, SystemVerilog, Bluespec SystemVerilog, or VHDL. Extra consideration for knowledge of device architectures or intermediate/back-end EDA tools... more

Aug 11 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

hardware description languages such as VHDL, Verilog, or SystemVerilog. This ... design opportunities include:• Digital system design using FPGAs and software defined... more

Aug 10 Digital Systems Design - Lead Intersil Austin, TX

limited to: - Design and implementation of Verilog RTL - Development of FPGA Emulation ... industry experience - RTL Verilog and System Verilog - FPGA experience; Xilinx -... more

Aug 08 Pre-Silicon Validation Engineer Intel Thousand Oaks, CA

not limited to: * Designing and debugging SystemVerilog-based verification testbenches ... desired * Proficient in Verilog / System Verilog * Experience in pre-silicon... more

Aug 08 Digital Verification Reqrouteinc.com Dallas, TX

verification with strong fundamentals on SYSTEM VERILOG (SV), UVM, Hands on experience in writing and reviewing validation test plans Experience building pre-silicon validation... more

Aug 07 Pre-Silicon Validation Engineer Job Intel Newbury Park, CA

not limited to: - Designing and debugging SystemVerilog-based verification testbenches ... desired - Proficient in Verilog / System Verilog - Experience in pre-silicon... more

Aug 07 C++ and System Verilog/UVM Engineer Hire IT People Marlborough, MA

Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. more

Aug 07 Fulltime opportunity for VLSI Design Verification Engineers Wipro California

experience. -Experience with one or more of: System Verilog, SVA, Vera . -Experience with ... or more of: OVM, VMM, RVM. -Familiar with Verilog or VHDL. Skills/Experience:... more

Aug 06 Sr. Staff Design Verification Engineer Commnexus Santa Clara, CA

programming ability in C, C , System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Aug 06 FPGA VERIFICATION ENGINEER - SWITCHING DIVISION (3 Georgia Department of Labor Alpharetta, GA

verification languages is required. SystemVerilog experience is preferred. ... oriented hardware verification languages, SystemVerilog is preferred. Knowledge and... more

Aug 06 Urgent job position for Asic Verification Qsolv San Jose, CA

through tapeoutExpert level knowledge of SystemVerilog, including object-oriented ... functional coverage constructs (covergoups, SystemVerilog assertions)Experience... more

Aug 05 Senior Member Technical Staff Mentor Graphics Incorporation Indiana

verification • Required: Strong Verilog/System Verilog Experience, Strong C PLI experience, Good Assembly understanding, Some bus protocol understanding ( e.g. PCI, AXI ) •... more

Aug 05 FPGA Verification Engineer Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Aug 05 VLSI Verification - System Verilog Mindlance Raleigh, NC

order - 252640 Title - VLSI Verification - System Verilog Location - Raleigh ,NC ... Skills/Experience: Must have experience in System Verilog and either UVM (preferred) or OV... more

Aug 02 Design Verification Engineer - Interconnect Middlesex Community College Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Aug 01 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Broadcom Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* Business Unit Broadband ... RTL design experience (VHDL/Verilog/SystemVerilog) and/or very strong OO... more

Jul 29 Jr. FPGA Engineer Talent Rif Chicago, IL

Qualifications FPGA infrastructure development Developing unit / system testbenches Test a ... offs Understanding of hardware architecture Verilog (SystemVerilog is a plus) Experience... more

Jul 29 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of... more

Jul 24 Hardware Verification Engineer (MemC/DDR PHY experience) (E1924523) QUALCOMM Raleigh, NC

experience *LI-SRC Keywords System Verilog, UVM, Verification, IP Verification, DDR, Memory Controller You will need to login into your profile to apply for this job. If you... more

Jul 24 BUS Verification Expert Randstad Technologies - New Cary, NC

UVM/SystemVerilog test bench architecture, SystemVerilog functional coverage, industry standard simulators. EEO Employer: Race, Religion, Color, Sex, Disability, National Origin,... more

Jul 21 Senior Staff Verification Engineer (UVM) Kforce Inc. San Jose, CA

Verilog AMS is a plus Very strong System Verilog programming skills. Solid ... Perl or Tcl Must have experience building SystemVerilog test-benches from scratch... more

Jul 15 Design Verification Engineer - Interconnect Artisan Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jul 10 Senior ASIC Design Engineer ( Frontend ) Radiant Systems San Diego, CA

data formats including timing, power, area, system performance, SDC, VCD, FSDB, SAIF, ... used hardware description languages such as Verilog, VHDL and System Verilog Strong... more

Jul 08 Senior Staff Digital Design Engineer Atmel San Jose, CA

and mixed-signal simulators * Knowledge of Verilog and/or System Verilog language for ... Skills * Knowledge and ability to use System Verilog Assertions * Knowledge and... more

Jul 07 ASIC Architect - Technologist Hitachi Global Storage Technologies San Jose, CA

other engineering departments including system architecture, hardware, and software ... and results Experience with Verilog/System Verilog, C/C++, linux, scripting... more

Jul 04 Member Consulting Staff Mentor Graphics Indiana

Optimization, code coverage and system Verilog language support Good Understanding ... structure, algorithm and familiarity with system Verilog/VHDL/TCL/TK Candidate should... more

Jun 30 Digital Design Engineer Inphi Thousand Oaks, CA

implementing RTL designs using Verilog/SystemVerilog; implementing verification test ... of digital and mixed-signal circuits; Verilog or System Verilog to verify functional... more

Jun 30 MTS ASIC Verification Design Engineer Cameron Resources Group Massachusetts

test libraries, software modeling, Verilog modeling, test development, ... caches Must be proficient in Verilog, System Verilog, C and C++, OVM/ UVM, Perl, Unix... more

Jun 27 RTL Designer Spectraforce Technologies East Brunswick, NJ

development using Verilog and SystemVerilog Creating test benches and ... simulations for functional validation using Verilog and System Verilog Working knowledge... more

Jun 20 Pre-Silicon Functional Validation Hillsboro, OR

members with methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to backbone (IOSF). PCIE background is a bonus which will help... more

Jun 20 Design Verification Engineer 2 AMD Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 17 FPGA Engineer III - Bothell Sonosite Washington

(VHDL, System Verilog, System C or C/C , scripting in Bash, Python, Perl, or Tcl). ��� Experience with ISO, FDA, or other regulated product development environments is a plus. ���... more

Jun 10 Digital Design Engineers (AMRD356-357) Fortinet Sunnyvale, CA

Verilog and System Verilog syntax constructs • Experience with DDR3/QDR/XAUI. • ... understanding of simulation and synthesis implications of various Verilog RTL... more

Jun 09 Sr Staff Engineer Seagate Minnesota

utilizing Unix, Linux, Synopsys Tools, and Verilog. Experience running large scale ... Experience designing in Verilog and/or System Verilog... more

Jun 06 Memory Subsystem Design Engineer Talarience Folsom, CA

and/or software architects to develop system models, evaluate memory system ... models and evaluation tools in C/C++, system Verilog and similar environments. more

May 31 Engineer, ASIC Design Verification Results Center Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 30 Engineer, ASIC Design Verification Marvell Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 28 Night Trade Support Engineer Chicago Financial Search Chicago, IL

development• Developing unit / system testbenches• Test ... of hardware architecture• Verilog (SystemVerilog is a plus)• Experience of full... more

May 20 IC Verification Engineer eTech Hi Simi Valley, CA

candidate will have experience using System Verilog, Specman e, Vera or System C) ... * Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.If interested... more

May 16 Engineer Circuit Design- 4 Abacus Service Redondo Beach, CA

with an emphasis on expertise in System Verilog and OVM/UVM methodology? MUST ... with an emphasis on expertise in System Verilog and OVM/UVM methodology. more

May 15 Engineer Circuit Design- 4 (5) Chipton Ross California

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... with an emphasis on expertise in System Verilog and OVM/UVM... more

Apr 28 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage ... experience Candidate SHOULD also have system verilog test bench experience. We need... more

Apr 25 Co-Op Engineer Amd | Seamicro Austin, TX

- Understanding and some experience with Verilog, C/C , Perl, and logic simulation is a re ... - Experience with SystemVerilog/OVM is a plus... more

Apr 09 SENIOR ASIC VERIFICATION ENGINEER NVIDIA Westford, MA

and system level verification - Expertise in System Verilog or similar HVL - Good debugging and problem solving skills - Perl and C/C++ programming language experience - Good... more

Apr 07 Principal Application Engineer Cadence Design Systems Austin, TX

e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience ... SystemVerilog, Specman e, VHDL, verilog Methodologies: Preferable experience in... more

Mar 25 DV -SoC Design Verification OVM/UVM Recruiting Engine (mls) San Diego, CA

not apply if you do not have experience in System Verilog and either UVM (preferred) or ... verification for cores and subsystem at the system level. The Verification Engineer will... more

Mar 24 Digital Design Engineer Google Mountain View, CA

the lowest levels of circuit design to large system design and see those systems all the ... Proficient in RTL / Logic / Verilog / System Verilog. * Successfully delivered... more

Mar 24 Senior Digital Design Engineer On Semiconductor Ireland, IN

in front-end design tools * Knowledge of systemVerilog is desirable. * Self driven individual and a good team player. * Diligent, detail-oriented, and willing to take initiative... more

Mar 12 Senior Verification Engineer Aba Search San Jose, CA

o Hardware modeling using UVM, Verilog, System Verilog or C/C++ o 6 + years of ... functional coverage o Expertise in System Verilog, OVM/UVM or Vera based tools o... more

Mar 12 ASIC Verification Engineer Systel Santa Clara, CA

like VMM, OVM, UVM Development will be done System Verilog Develop test plans, execute ... environment using Constraint Random, SystemVerilog Assertions Strong knowledge of... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

SICs Knowledge of video codec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC,... more

Mar 04 Verification Group Manager Direct Staffing Austin, TX

products. Strong background with HDLs (e.g. Verilog, VHDL), HVLs (e.g. SystemVerilog/OVM, ... models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing... more

Feb 21 Verification Engineer Altera San Jose, CA

You will write test plans and implement SystemVerilog/UVM based verification ... with coverage driven verification using SystemVerilog test bench development using... more

Feb 20 Applications Engineer - Verification Tabula Santa Clara, CA

Skills: 3+ years of industry experience Verilog/SystemVerilog coding experience UVM/OVM Assertion-based verification Creation of verification environments that implement... more

Feb 13 Principal Verification Engineer Aba Search San Jose, CA

and development and modeling using UVM, SystemVerilog, Verilog. EXPERIENCE o ... verification languages OVM/UVM/System Verilog/C++ o Expertise in putting... more

Feb 07 Programmable Logic Engineer Viasat Atlanta, GA

methods using Verilog, and/or System Verilog hardware description language * ... including Verilog and/or System Verilog hardware description languages. Your... more

Feb 06 Senior Staff Design Engineer Xilinx San Jose, CA

· Expert level understanding of Verilog, SystemVerilog, Timing Constraints and Digital Design principles. · Hands on experience of Front End Design and Implementation steps... more

Jan 22 R&D Engineer, Sr I Synopsys Sunnyvale, CA

Working knowledge of Verilog/SystemVerilog/VHDL, ASIC design and verifications flows • Knowledge/experience with any of the following would be a plus: massively scalable... more

Jan 08 Sr. R&D Engineer Real Intent California

of the following fields: GUI, Verilog/System Verilog/VHDL Compilation, Synthesis ... and verification flow, working knowledge of Verilog, VHDL, and SystemVerilog... more

Dec 31 FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL Darwin Recruitment Newport Beach, CA

FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL FPGA/ASIC Designer - Darwin Recruitme ... or equivalent academic qualification. System Verilog or Specman Cadence E... more

Dec 02 Verification Engineer Cypress Semiconductor Colorado Springs, CO

Skills Digital Verification using System Verilog Experience using OVM or UVM, ... Experience Digital Verification using System Verilog Experience using OVM or UVM,... more

Nov 30 ASIC Verification Engineer - Boise, Idaho Job Micron Boise, ID

ASIC verification, working closely with the system group, architects, design and ... developing Re-Usable Test Benches in SystemVerilog Additional Skills: - Knowledge... more

Jun 05 Engineer, ASIC Design Verification Marvell Technology Group Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

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