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Nov 13 System Verilog OVM/UVM Systems Pros Minneapolis, MN

system verilog OVM UVM RTL Embedded processor subsystems memory bus controller 5+ years experience with system verification more

Nov 05 Systems Verilog Engineer Tekpartners, A P2p Company Hillsboro, OR

test benches and functional tests in system Verilog. • Prepare specifications, ... Verilog, System Verilog, System C, using OVM/UVM methods. • Knowledge of Perl, Python... more

More Job Postings from the Web
Nov 23 Graphics Top Level RTL Designer Apple Austin, TX

Proficiency in: revision control systems, Verilog, VHDL, verification, lint checks, and multi-clock domain designs. Efficient with simulation and debugging tools. Strong... more

Nov 23 Lead Design Verification Electrical Engineer Insiderjobboard.com Vancouver, WA

the functional verification of ASICs using System Verilog and UVM methodologies. She/he ... ASIC verification infrastructure in System Verilog and pref Specman-e Hands-on... more

Nov 23 Junior Graphics Emulation Execution Engineer Apple Austin, TX

report status * Participate in debug of system by capturing waveforms and writing ... languages are C, Perl, Ruby, System Verilog) Graphics knowledge a plus; 3D... more

Nov 23 Lead Design Verification Electrical Engineer Compound Photonics Vancouver, WA

the functional verification of ASICs using System Verilog and UVM methodologies. She/he ... ASIC verification infrastructure in System Verilog and pref Specman-e Hands-on... more

Nov 21 Verification Test Engineer Micro Tech Staffing Group Nashua, NH

rate and execute a plan for verification and validation of full digital/analog/firmware/testability system. Must have working knowledge of Verilog, System Verilog, C, and... more

Nov 21 Processor Core IP Development Manager QUALCOMM Austin, TX

verifies complex interconnect IP utilizing Verilog and UVM/System Verilog. The manager ... UVM, System Verilog, C/C++, Perl, Tcl, Unix scripting, formal verification, constrained-ra... more

Nov 21 High Speed SERDES Verification Engineer - Experienced Only QUALCOMM Raleigh, NC

- Strong knowledge of HVLs (VERA, e, System Verilog), HDLs (Verilog, VHDL), C/C++ ... - Experience with environments leveraging Verilog-AMS for mixed signal verification -... more

Nov 21 Internship-to-hire - Design Verification Quantum Solution Santa Clara, CA

coverage driven verification, system & architectural compatibility ... verification * Hands on experience with System Verilog, NTB/VERA, SPECMAN, C/C++, Perl... more

Nov 21 Verification Engineer Tata ELXSI Folsom, CA

dation or design experience in Serial IOs, like PCI-e, MIPI, etc. Gate level simulations experience. Mainly strong debug and problem solving skills. OVM, System Verilog, Perl,... more

Nov 21 Staff Design Engineer Mainz Brady Group San Jose, CA

knowledge of verification methodology System Verilog experience Are you available? Please ... httpwww.mbg.commobileapps Verilog AND "staff design engineeer" AND... more

Nov 21 Principal Application Engineer Cadence Design Systems Austin, TX

e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience ... Languages: SystemVerilog, Specman e, VHDL, verilog Methodologies: Preferable experience in... more

Nov 20 SENIOR DESIGN ENGINEER Judge Group San Jose, CA

Coding of designs and algorithms in Verilog and/or C Complete design cycle of simulation, ... *Good knowledge of verification methodology- *System Verilog experience - Salary:... more

Nov 20 IP Design Verification Manager Altera Milpitas, CA

environment components utilizing UVM/System Verilog, creates test plans from ... verifications capabilities with UVM, System Verilog, constrained-random testing... more

Nov 20 FPGA/ASIC Engineer General Dynamics Scottsdale, AZ

BSEE/MSEE/BSCS/MSCS or Equivalent Strong proficiency in SystemVerilog, Verilog, VHDL, C/C+ ... design verification using System Verilog. Additional preferential skills are Verilog... more

Nov 20 Sr. ASIC/FPGA Verification Engineer General Dynamics Scottsdale, AZ

* Strong proficiency in SystemVerilog, Verilog, VHDL, C/C++, Perl, and UNIX ... design verification using System Verilog. Additional preferential skills are Verilog... more

Nov 19 CPU Sub-System Verification Engineer (Sr/Staff Engineer) Randstad Technologies - New Cary, NC

entry, simulation, and debug tools -System Verilog experience, including use of UVM/OVM ... test code using ARM assembly and System Verilog -Run simulation and coverage tools... more

Nov 19 Electrical Engineer - Digital Logic Design National Engineering Resources Minneapolis, MN

Engineering with 1+ years of experience FPGA Verilog HDL (VHDL) Digital Logic Design and ... object orientated design concepts including System Verilog or System C. Experience doing... more

Nov 17 SOC Design Verification Intern Intel Austin, TX

of various interfaces using Verilog, VHDL, SystemVerilog, Specman and C-programming ... - Minimum of 3 months experience with Verilog / System Verilog *Preferred Qualifications:*... more

Nov 14 Electrical Engineer (Senior Design Engineer) (1626.24) Soft Machines Santa Clara, CA

performing architectural compliance, Verilog/System Verilog coding, VLSI Logic design, ... Verilog, VHDL, or Assembly Language; 8. C, System Verilog, or Perl Scripting; 9. more

Nov 13 Design Verification and Post Silicon Validation (low power design exp) Encore Semi San Diego, CA

System Verilog Assertions (SVA), and System Verilog Testbench (SVTB). • Experience ... of industry experience in system integration and troubleshooting, including hands-on... more

Nov 12 Verilog Engineer Position Fabergent Folsom, CA

JD: Strong Expertise in System Verilog, UVM/OVM, or high-level verification frameworks Generation of Testbench components, Assertions, Monitors etc. Identification and development... more

Nov 12 Design Engineer Intern Hillsboro, OR

following activities: - logic design using System Verilog - functional logic ... of 3 months experience with verilog OR system verilog - Minimum of 3 months... more

Nov 12 Validation or Verification Engineer opportunity with our direct client Yugadytechnologies Folsom, CA

with USB 3.0 IO experience Skills: System Verilog, OVM are must Job description: ... coverpoints. Experienced candidates with System Verilog, OVM are must Highly preferred... more

Nov 12 Lead Digital Verification Engineer Texas Instrutments Dallas, TX

digital test-benches in System Verilog (or UVM) to apply constrained random stimulus ... to tape-out • Verilog and System Verilog • Advanced verification methodologies such... more

Nov 11 Functional Verification Engineering Professional IBM Essex Junction, VT

verification techniques to validate that Verilog core Intellectual Property (IP) ... Coding is done with System Verilog, and Open Verification Methodology (OVM)/ Universal Ver... more

Nov 11 Engineer, Sr Principal - IC Design Verification Broadcom San Jose, CA

level. • Experience using SystemVerilog, VMM or UVM. • Familiar with System Verilog Assertions. • Strong experience in ASIC design verification flows and DV methodologies. •... more

Nov 09 Intern: Hardware Engineer (Routing Systems) Juniper Networks Sunnyvale, CA

by modifying or using existing Verilog/System Verilog test benches Basic Qualifications: * Basic knowledge of Unix/Linux operating systems * Some experience with a programming... more

Nov 09 Design Verification Lead Commnexus Santa Clara, CA

programming ability in C, C++, System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Nov 08 Sr. Design Engineer AMD Austin, TX

System Verilog/UVM • Developing System Verilog/UVM tests • Analyzing and debugging ... Key skills: • System Verilog/UVM, C/C++, object oriented programming, • Perl or equivalent... more

Nov 08 Verification Engineer Zodiac Solutions Folsom, CA

with USB 3.0 IO experience Skills; System Verilog, OVM Verification of 2LM-FMSS ... coverpoints. Experienced candidates with System Verilog, OVM is a must. Highly... more

Nov 07 Lab Technician Testing - H/W &S/W Online Technical Services Santa Clara, CA

Verilog expertise; System Verilog and VHDL knowledge is a plus Experience: • At least 3 years experience in a lab technician or characterization engineer role • Understanding... more

Nov 06 System of a Chip (SOC) Architect Amtec Engineering Hillsboro, OR

* MUST HAVE - proficient in System Verilog, UVM or OVM or equivalent * MUST HAVE ... of multi-core SoC memory management system design and verification * Working... more

Nov 06 Engineer, Verification Design Results Center Santa Clara, CA

and test benches. . Understanding of System Verilog test methodology is a must. ... ARM SOC embeded system and AMBA. . Understanding of System Verilog is a must. more

Nov 06 System of a Chip (SOC) Architect Amtec Human Capital Hillsboro, OR

an ARM processor, multiple DSPs, memory sub-system, 802.11 baseband and MAC, and digital ... HAVE - proficient in System Verilog, UVM or OVM or equivalent// 10 out 10 - verilog •... more

Nov 05 Verification Engineer - Immediate Interviews Icon Solutions Folsom, CA

with USB 3 0 IO experience Skills System Verilog OVM Verification of 2LM-FMSS ... coverpoints Experienced candidates with System Verilog OVM is a must Highly preferred... more

Nov 05 ASIC Architect (Senior / Principal) Ericsson San Jose, CA

pipeline design Strong knowledge of Verilog/System-Verilog for implementation Good Network processing domain knowledge such as: Various packet header encapsulation format for L2,... more

Nov 04 Lead Design Verification Engineer Oracle Santa Clara, CA

high performance SOC - Develop & maintain System Verilog testbenches - Develop & ... Architecture • Experience coding Verilog, SystemVerilog and one of UVM/OVM/VMM •... more

Nov 04 Engineer, Verification Design Marvell Technology Group Santa Clara, CA

rage SOCs for mobile storage systems. . Familiar with ASIC flow from spec to RTL to tape-out . Familiar with ARM SOC embeded system and AMBA. . Understanding of System Verilog is... more

Nov 04 Sr. Staff Design Verification Engineer Commnexus Santa Clara, CA

programming ability in C, C++, System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Nov 04 Senior Digital Design Engineer - #102 Ngcodec Sunnyvale, CA

a written spec and/or software model Expert Verilog RTL designer Proficient C/C++ coder ... synthesizing and implementing designs on FPGAs System Verilog and SystemVerilog... more

Nov 03 ASIC Verification engineer UVM S and D Engineering Solutions Santa Clara, CA

from scratch and be comfortable with System Verilog and UVM Needs to be methodical in his her approach and have proven track record of successfully completed participated in large... more

Nov 03 system verilog ovm uvm Systems Pros Denver, CO

asic verification system verilog ovmuvm rtl perl script Vinnie Majeski Systems Pros Inc 76 Treble Cove Road Bldg 2 Billerica MA 01862 Phone 800 891-2255 ext 1141 Fax 800717 6121 more

Nov 03 Principal Digital Design Engineer Inphi Santa Clara, CA

specification definition, Verilog coding, synthesis and timing closure to ... products incorporating FEC; Verilog, System Verilog, Perl, Unix Shell; RTL and gate... more

Nov 03 Sr. Design Engineer Amd | Seamicro Austin, TX

System Verilog/UVM • Developing System Verilog/UVM tests • Analyzing and debugging ... Key skills • System Verilog/UVM, C/C++, object oriented programming, • Perl or equivalent... more

Oct 31 Design Engineer Horizontal Integration San Jose, CA

of logic fundamentals Excellent knowledge of Verilog Capable of writing ... in statistical methods Good knowledge of verification methodology System Verilog... more

Oct 29 Principal ASIC Verification Engineer Hitachi Global Storage Technologies San Jose, CA

and consumer electronics and automotive system manufacturers to store the avalanche ... verification language such as System Verilog, Vera, or Specman and methodologies... more

Oct 28 Director of Software Engineering San Jose, CA

creative problem solving. Expertise in IP and SOC design and verification process and requirements Expertise and familiarity with HDL, C, C++, System Verilog, UVM and other... more

Oct 28 Senior ASIC Verification Engineer with Security Clearance 2020itservices Fort George G Meade, MD

and creating test benches. Expertise in System Verilog critical Experience with VMM,OVM or UVM Experience with Mentor QuestaSim Simulation tools Experience with Linux and Perl... more

Oct 27 ASIC Verification Engineer II (University Hire) Job SanDisk Milpitas, CA

be closely working with the RTL designers, system architect and firmware team to develop ... skills * Hands on experience in Verilog and System Verilog is plus. * Strong... more

Oct 27 Microprocessor Verification (DV) Engineer Quantum Solution Santa Clara, CA

coverage driven verification, system & architectural compatibility ... verification * Hands on experience with System Verilog , NTB/VERA, SPECMAN, C/C++ and... more

Oct 27 SOC Design Verification Engineer Collabera San Diego, CA

and assertion languages: RTL, Verilog, System Verilog or Vera, System Verilog Assertions (SVA) etc. • Familiar with Hardware Verification Methodologies : RVM or VMM or OVM or UVM... more

Oct 26 Sr Staff Engineer Seagate Shakopee, MN

utilizing Unix, Linux, Synopsys Tools, and Verilog. * Experience running large scale ... * Experience designing in Verilog and/or System Verilog... more

Oct 24 Principal Engineer, Digital Design Fortinet Sunnyvale, CA

Innovative implementation of latest Verilog and System Verilog syntax constructs ... understanding of simulation and synthesis implications of various Verilog RTL... more

Oct 22 Verification Engineer, Cache- Eng II(OVM/UVM) Collabera Raleigh, NC

Skills / Experience: System Verilog, OVM, UVM, Object Oriented Programming, power experien ... experience Category:IT System Verilog, OVM, UVM, Object Oriented... more

Oct 21 Digital Design Engineer Nxp Semiconductors Tempe, AZ

be required using verilog and system verilog. This position requires excellent communication and problem solving skills. At least 5 years of digital design experience and... more

Oct 21 Verification Engineer Yoh Mesa, AZ

Experience with Verilog and VHDL UVM/OVM experience Expert in debugging complex mixed doma ... Embedded design experience is preferred System Verilog Experience is preferred... more

Oct 20 Verification Engineers Novus Resources Raleigh, NC

System Verilog, OVM/UVM, Functional Coverage, bus verification experience is a bonus ... bug fixes and feature development on complex system bus with cache coherency. Looking for... more

Oct 15 Software Engineer I F5 Networks Spokane, WA

Work with TCP/IP networking system architects to understand the system level perspective a ... skills. Desired Qualifications System Verilog design and verification experience. more

Oct 14 Engineer, Senior Staff Verification Marvell Technology Group Austin, TX

in design verification with System Verilog and UVM. Knowledge of other verification disciplines like Emulation, FPGA is a big plus. Must experience with both block level and... more

Oct 14 Hardware - Digital Engineer - Sr. Plexus Boulder, CO

simulation * HDL coding (VHDL, Verilog, System Verilog) * Operating general lab equipment (DMM, oscilloscope, logic analyzer, device programmers) * Previous project leadership a... more

Oct 14 Digital Verification Engineer Cyient Charlotte, NC

understanding of Object Oriented System Verilog principles including OVM or UVM. ... OVM or UVM (or at least VMM), verification (systemverilog, ovm/uvm/vmm, random... more

Oct 12 Principal/Sr. Principal RTL Verification Engineer (SystemVerilog/UVM/ARM) Ethan Alexander Group Sunnyvale, CA

environment development using System Verilog based methodologies (OVM/UVM) ... assembly tests Experience using the HDLs (Verilog, System Verilog) Experience using HVL... more

Oct 08 ASIC Verification Sage IT Chandler, AZ

System Verilog OVM/UVM, Good experience in System Verilog OVM/UVM based verification environment development, Sound understanding of Random and constrained random-verification... more

Oct 08 Verification Engineer Enterprise Solutions Chandler, AZ

Verification Methodology - OVM(Mandatory) System Verilog - SV(Mandatory) VLSI HVL Verification As a Lead, you are responsible for managing a small team of analysts, developers,... more

Oct 08 Pre Silicon Verification Engineer Sage IT Hudson, MA

using System Verilog UVM, Good experience in System Verilog –UVM based verification environment development, Sound understanding of Random and constrained random-verification... more

Oct 08 Sr. Performance/Functional Modeling Engineer Job Micron Milpitas, CA

modeling experience (Verilog, System Verilog, System C, C++ or equivalent languages). - Familiarity with industry standard modeling techniques and Objected Oriented Programming. -... more

Oct 06 Digital Design Engineer Fusion408 Westlake Village, CA

level integration and verification using Verilog and system Verilog, synthesis and ... processing products. * Solid knowledge in Verilog and system Verilog * Solid knowledge... more

Oct 06 Senior Staff Digital Design Engineer Fusion408 San Jose, CA

* Architecture of Digital Filters * RTL Design using Verilog/System Verilog * Top-level Synthesis &Static Timing Analysis (STA) * Digital Design for Ultra-Low Power applications *... more

Oct 03 Applications Engineer Tabula Santa Clara, CA

complex hardware-software systems · Verilog/SystemVerilog/VHDL coding experience · ModelSim/Questa and/or NCSim experience · Customer facing experience for pre/post-sales support... more

Oct 02 Principal Engineer Leading Manufacturer of Computer Hardware Santa Clara, CA

of architectural specification documents, system level models, complex circuit design, ... with the VCS, Vera verification language, System Verilog, objected-oriented... more

Sep 26 R&D Engineer IC Design 3 Avago Technologies Indiana

in 2-3 projects. Good understanding of System Verilog is a must. Should have experience in developing and maintaining testbench. The candidate should have experience in gate level... more

Sep 23 Functional Verification Engineer - Pre-Silicon: 234296 Core-tech Santa Clara, CA

System Verilog OVM/UVMc. Good experience in System Verilog - OVM/UVM based verification ... architectureb. Creating test scenarios(System Verilog OVM)c. Work with RTL teams to... more

Aug 29 Entry Level Digital Design Engineer Cirrus Logic Austin, TX

Primary activities include: design using Verilog, logic simulation, functional ... Dividers, and Sate Machines Strong Skills System Verilog Applied to Functional... more

Aug 11 FPGA RTL Design Engineer Real Staffing San Jose, CA

of the following responsibilities: Producing system wrappers for FPGAs and porting Verilog ... Required Skills: Hardware languages: Verilog, VHDL, System Verilog. Synopsys... more

Aug 05 Senior Member Technical Staff Mentor Graphics Indiana

verification • Required: Strong Verilog/System Verilog Experience, Strong C++ PLI experience, Good Assembly understanding, Some bus protocol understanding ( e.g. PCI, AXI ) •... more

Jul 31 Principal Engineer Seagate Santa Clara, CA

of architectural specification documents, system level models, complex circuit design, ... VCS, Vera verification language, System Verilog, objected-oriented programming, C/C++... more

Jul 15 Sr. Digital Camera Design Engineer Raytheon Goleta, CA

Verification flows using Vera or System Verilog for ASICs or FPGAs * Prior experience ... * Experience with Android operating system and application development. *... more

Jul 14 DFX validation engineer Intel Israel, PR

validation environments based on System Verilog and work with RTLdesigners and post ... verification/validation methods, Specman language, SystemVerilog, DFX design &... more

Jul 01 IC Design Verficiation Engineer Avago Technologies Allentown, PA

processor products. The candidate will use SystemVerilog, Verilog and other Unix ... using behavioral simulation using System Verilog, VMM or UVM methodologies. *... more

Jun 27 Engineer, Senior Staff Marvell Santa Clara, CA

1.MSEE 2.Verilog RTL and circuit behavioral modeling 3.Design verification, logic ... verification skills 4.Perl, Verdi, System Verilog, Matlab, UVM/OVM experience... more

Jun 20 Design Verification Engineer 2 AMD Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 17 FPGA Engineer III - Bothell Sonosite Washington

(VHDL, System Verilog, System C or C/C , scripting in Bash, Python, Perl, or Tcl). ��� Experience with ISO, FDA, or other regulated product development environments is a plus. ���... more

Jun 13 Design Verification Engineer 2 Amd | Seamicro Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 06 Memory Subsystem Design Engineer Talarience Folsom, CA

and/or software architects to develop system models, evaluate memory system ... models and evaluation tools in C/C++, system Verilog and similar environments. more

May 31 Engineer, ASIC Design Verification Results Center Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 30 Engineer, ASIC Design Verification Marvell Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

Apr 23 Lead Engineer Mentor Graphics Indiana

e to ARM assembly language, ARM processor architecture, ARM Fast Models, QEMU are a plus. Exposure to Verilog/VHDL/System Verilog, SystemC and functional verification tools like... more

Apr 21 VERIFICATION ENGINEER NVIDIA Santa Clara, CA

- Expertise in System Verilog and/or UVM highly desirable. - Scripting knowledge. - Good debugging and problem solving skills. - Good communication skills and ability & desire to... more

Mar 25 DV -SoC Design Verification OVM/UVM Recruiting Engine (mls) San Diego, CA

not apply if you do not have experience in System Verilog and either UVM (preferred) or ... You will be contributing to the verification effort of a complex chip, sub-system and/or b... more

Mar 24 Digital Design Engineer Google Mountain View, CA

the lowest levels of circuit design to large system design and see those systems all the ... * Proficient in RTL / Logic / Verilog / System Verilog. * Successfully delivered... more

Feb 24 SoC Design Verification Engineer Altera Austin, TX

to the following: Developing unit/core/system level testbench, BFMs (Bus Functional ... methodologies (such as UVM, OVM, System Verilog, constrained-random stimulus... more

Feb 13 Principal Verification Engineer Aba Search San Jose, CA

and development and modeling using UVM, SystemVerilog, Verilog. EXPERIENCE o ... verification languages OVM/UVM/System Verilog/C++ o Expertise in putting... more

Jan 08 Sr. R&D Engineer Real Intent California

of the following fields: GUI, Verilog/System Verilog/VHDL Compilation, Synthesis ... and verification flow, working knowledge of Verilog, VHDL, and SystemVerilog... more

Jan 07 ASIC Verification Engineer Systel Santa Clara, CA

like VMM, OVM, UVM Development will be done System Verilog Develop test plans, execute ... environment using Constraint Random, SystemVerilog Assertions Strong knowledge of... more

Jan 07 Senior Verification Engineer Aba Search San Jose, CA

o Hardware modeling using UVM, Verilog, System Verilog or C/C++ o 6 + years of ... functional coverage o Expertise in System Verilog, OVM/UVM or Vera based tools o... more

Dec 31 FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL Darwin Recruitment Newport Beach, CA

FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL FPGA/ASIC Designer - Darwin Recruitme ... or equivalent academic qualification. System Verilog or Specman Cadence E... more

Dec 12 Senior Product Applications Engineer2 Xilinx San Jose, CA

with RTL design languages including Verilog, VHDL, and System Verilog, as well as ... software design process with regard to system bring up, and hardware/software debug. more

Dec 02 Electrical Design Engineer Cypress Semiconductor San Jose, CA

knowledge of Verilog HDL for synthesis and modeling • Good skills in a programming ... formal verification • System Verilog • Gate level verification with timing Cypress is... more

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