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Oct 29 Systems Verilog Engineer Tekpartners, A P2p Company Hillsboro, OR

plans, test benches and functional tests in system Verilog. Prepare specifications, ... Skills Experience with Verilog, System Verilog, System C, using OVM/UVM methods. more

More Job Postings from the Web
Oct 31 ASIC Verification engineer (UVM) S & D Engineering Solutions Santa Clara, CA

from scratch, and be comfortable with System Verilog and UVM. Needs to be ... citizen, ASIC Verification engineer, System Verilog, UVM, Experience building... more

Oct 31 FPGA Engineer - Quant Prop Trading Firm Selby Jennings Houston, TX

FPGA architecture design in VHDL and/or Verilog Experience with FPGA connectivity through ... science subject Experience writing system Verilog for synthesis and/or simulation... more


and system level verification - Expertise in System Verilog or similar HVL - Good debugging and problem solving skills - Perl and C/C++ programming language experience desirable -... more

Oct 30 Verification Engineer Aclat Folsom, CA

of failing test cases. Improve coverage and write coverpoints. Pre-silicon Verification with USB 3.0 IO experience Experienced candidates with System Verilog, OVM is a must. more

Oct 30 Sr Product Applications Engineer2 Xilinx Longmont, CO

including Verilog,. VHDL, and System Verilog. The role would include in-depth analysisof customer designs and constraints to uncover potential synthesis bottlenecks and areas for... more

Oct 30 SOC Verification Engineer Dbsi Services Raleigh, NC

all necessary tools and scripts to enable system-level testing in an automated fashion. ... of HVLs(VERA/e/System Verilog), HDLs(Verilog/VHDL), C/C++ Must have hands-on... more

Oct 30 FPGA/ASIC Engineer General Dynamics Scottsdale, AZ

BSEE/MSEE/BSCS/MSCS or Equivalent Strong proficiency in SystemVerilog, Verilog, VHDL, C/C+ ... design verification using System Verilog. Additional preferential skills are Verilog... more

Oct 30 Verification Engineer Job Yoh Mesa, AZ

Possess: - Verification Methodologies- VHDL- Verilog What You'll Be Doing: - Verification ... Embedded design experience is preferred- System Verilog Experience is preferred-... more

Oct 30 System Verification/Validation Engineer Incoln Folsom, CA

Position Experienced candidates with System Verilog, OVM is a MUST. Verification of 2LM-FMSS includes: · Code and execute test sequences and testcases to verify different... more

Oct 30 Sr. ASIC/FPGA Verification Engineer General Dynamics Scottsdale, AZ

* Strong proficiency in SystemVerilog, Verilog, VHDL, C/C++, Perl, and UNIX ... design verification using System Verilog. Additional preferential skills are Verilog... more

Oct 29 Senior Member of Technical Staff, IC Design Maxim Integrated Products San Jose, CA

signal devices Design digital blocks using System Verilog and other HDL languages Produce detail documentation and analysis for the design Use state of the art verification tools... more

Oct 29 SENIOR DESIGN ENGINEER Judge Group San Jose, CA

Coding of designs and algorithms in Verilog and/or C Complete design cycle of simulation, ... of verification methodology *System Verilog experience Please email qualified... more

Oct 29 Principal ASIC Verification Engineer Hitachi Global Storage Technologies San Jose, CA

and consumer electronics and automotive system manufacturers to store the avalanche ... verification language such as System Verilog, Vera, or Specman and methodologies... more

Oct 28 FPGA Engineer -5 years Experience - Chicago, IL Manufacturing Automative Services San Francisco, CA

of hardware architecture Verilog (System Verilog is a plus) Experience of full ... FPGA infrastructure development Developing unit / system test benches Test... more

Oct 28 Senior ASIC Verification Engineer with Security Clearance 2020itservices Fort George G Meade, MD

and creating test benches. Expertise in System Verilog critical Experience with VMM,OVM or UVM Experience with Mentor QuestaSim Simulation tools Experience with Linux and Perl... more

Oct 28 Director of Software Engineering San Jose, CA

creative problem solving. Expertise in IP and SOC design and verification process and requirements Expertise and familiarity with HDL, C, C++, System Verilog, UVM and other... more

Oct 27 Design Verification and Post Silicon Validation (low power design exp) Encore Semi San Diego, CA

System Verilog Assertions (SVA), and System Verilog Testbench (SVTB). • Experience ... of industry experience in system integration and troubleshooting, including hands-on... more

Oct 27 Engineer, Senior ASIC Design Verification Marvell Technology Group Santa Clara, CA

* Candidate should be familiar with some of the following; System Verilog, Verilog, VCS/NCsim, C-language * Candidate must show a strong knowledge in the development of... more

Oct 27 ASIC Verification Design Engineer Johnson Service Group Sunnyvale, CA

experience and background in RTL-based Verilog and System Verilog high speed digital ... Substantial programming experience in C C Verilog System Verilog Able to create... more

Oct 27 Microprocessor Verification (DV) Engineer Quantum Solution Santa Clara, CA

coverage driven verification, system & architectural compatibility verification ... * Hands on experience with System Verilog , NTB/VERA, SPECMAN, C/C++ and Perl *... more

Oct 27 Graphics Software Engineer Apple Orlando, FL

with scripting, DPI, Verilog/VHDL, Specman/System Verilog, design verification methodology and tools a plus * Team leadership experience a plus * Excellent communication skills... more

Oct 27 Sr Staff ASIC Verification Eng Job SanDisk Milpitas, CA

development * Validation of SoC design and system level use case and performance ... latest verification methodologies System Verilog and UVM * Must have hands on... more

Oct 26 FPGA Solutions Engineer (DCG) Hillsboro, OR

in hardware development using VHDL or Verilog or System Verilog * Familiarity with ... of CPU micro-architecture and computer system architecture, including cache... more

Oct 25 Intern - IC Simulation Broadcom San Diego, CA

preferred: C++); With interest in System Verilog simulation, debug work and UVM/Class ... UVM/VMM , sytem verilog knowledge is a plus... more

Oct 24 Sr. Verification Engineer APN Software Services San Diego, CA

A solid working knowledge of Verilog, SystemVerilog, and UVM. A working knowledge ... Regards, Vikas digital circuits, Verilog, System Verilog, UVM, Cadence... more

Oct 24 Principal/Sr. Principal RTL Verification Engineer (Processor) Applied Micro Circuits Sunnyvale, CA

environment development using System Verilog based methodologies (OVM/UVM) * ... assembly tests * Experience using the HDLs (Verilog, System Verilog) * Experience using... more

Oct 24 Principal Engineer, Digital Design Fortinet Sunnyvale, CA

Innovative implementation of latest Verilog and System Verilog syntax constructs ... understanding of simulation and synthesis implications of various Verilog RTL... more

Oct 24 Sr Electrical Engineer Butler America Cedar Rapids, IA

the verification of RTL blocks using VHDL or System Verilog. * Proficiency using ASIC ... constrained random, functional coverage, SystemVerilog) * ASIC / FPGA lab validation... more

Oct 22 Verification Engineer, MTS Altera San Jose, CA

Strong background in C/C++, System Verilog, VMM/UVM verification methodology, verification ... in programmable logic solutions, enabling system designers and semiconductor companies... more

Oct 22 Verification Engineer, Cache- Eng II(OVM/UVM) Collabera Raleigh, NC

Skills / Experience: System Verilog, OVM, UVM, Object Oriented Programming, power experien ... or equivalent experience Category:IT System Verilog, OVM, UVM, Object Oriented... more

Oct 22 Verification Engineer II US Tech Solutions Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... High level verification languages (OVM/UVM/System Verilog) Strong embedded design... more

Oct 22 Verification Test Engineer Micro Tech Staffing Group Nashua, NH

rate and execute a plan for verification and validation of full digital/analog/firmware/testability system. Must have working knowledge of Verilog, System Verilog, C, and... more

Oct 21 Digital Design Engineer Nxp Semiconductors Tempe, AZ

be required using verilog and system verilog. This position requires excellent communication and problem solving skills. At least 5 years of digital design experience and ideally... more

Oct 20 Verification Engineers Novus Resources Raleigh, NC

  System Verilog, OVM/UVM, Functional Coverage, bus verification experience is a bonus ... fixes and feature development on complex system bus with cache coherency. Looking for... more

Oct 20 Sr Design Verification Engineer Bhi Energy |sun Technical Austin, TX

HDLs (e.g. Verilog, VHDL) and HVLs (e.g. System Verilog/OVM, UVM, AVM, Vera, e) ... models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing... more

Oct 18 ASIC Verification Engineer CAE Recruiters Lowell, MA

languages: o working knowledge of verilog is a must; system-verilog is a plus • Working knowledge of C programming; C++/OO coding principles a plus • Scripting and automation... more

Oct 17 ASIC Architect (Senior / Principal) 1 Ericsson San Jose, CA

other functional block Write up the system architecture specification that base on the ... design Strong knowledge of Verilog/System-Verilog for implementation Good Network... more

Oct 16 Verification Engineer Tekpartners, A P2p Staffing Company Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... High level verification languages (OVM/UVM/System Verilog) Strong embedded design... more

Oct 16 Engineer, Senior Staff Verification Marvell Austin, TX

in design verification with System Verilog and UVM. Knowledge of other verification disciplines like Emulation, FPGA is a big plus. Must experience with both block level and... more

Oct 16 Engineer, Senior Staff Verification Results Center Austin, TX

in design verification with System Verilog and UVM. Knowledge of other verification disciplines like Emulation, FPGA is a big plus. Must experience with both block level and... more

Oct 15 Verification Engineer Evo Phoenix, AZ

REQUIREMENTS : EXPERT in HDL development (Verilog and VHDL) both in design and ... high-level verification languages (OVM/UVM/System Verilog) Strong embedded design... more

Oct 15 Software Engineer I F5 Networks Spokane, WA

Work with TCP/IP networking system architects to understand the system level perspective a ... skills. Desired Qualifications System Verilog design and verification experience. more

Oct 15 DDR Silicon Validation Engineer Apple Santa Clara, CA

in C/C++ * Experience with Verilog/System Verilog * International Travel Required * Description: Working with design, verification and integration engineers to ensure memory... more

Oct 14 SoC Verification Engineer : C/C++, TCP, DMA, DDR, AMBA Xpeerant Raleigh, NC

of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++ - Must have hands-on ... -Extensive UVM/System verilog skills, as well as exposure to DDR, I2C, AMBA, and PCIe test... more

Oct 14 Verification Engineer - 7942 eTech Resources Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... High level verification languages (OVM/UVM/System Verilog) :Strong embedded design... more

Oct 14 Palladium Engineer : Palladium, FPGA, VHDL, Verilog Xpeerant Raleigh, NC

s of industry experience. FPGA based emulation with direct Palladium experience required. Excellent verbal and documentation skills Experience: Verilog and/or VHDL, System Verilog... more

Oct 14 Verification Engineer III (3867) Randstad Technologies - New Chandler, AZ

shall be expert in HDL development (Verilog and VHDL) both in design and ... level verification languages (OVM/UVM/System Verilog) •Strong embedded design... more

Oct 14 Digital Verification Engineer Cyient Raleigh, NC

understanding of Object Oriented System Verilog principles including OVM or UVM. ... OVM or UVM (or at least VMM), verification (systemverilog, ovm/uvm/vmm, random... more

Oct 13 Pre-Si Verification engineer Santa Clara, CA

Scoreboard. * 7 years' experience working in System-Verilog OVM, since most of the VIP collaterals is developed in SV-OVM. * The candidate should be able to work independently... more

Oct 13 Advanced Memory Systems RTL Lead Engineer Job Micron Boise, ID

will include working with the System Architecture team to specify the ... have: - Proficiency with Verilog, and/or System Verilog, Linux OS, and associated... more

Oct 13 Engineer: Verification - III Experis Chandler, AZ

REQUIRED EXPERIENCE/SKILLS: BSEE degree Expert in HDL development (Verilog and VHDL) both ... High level verification languages (OVM/UVM/System Verilog) Expert in debugging complex... more

Oct 13 Lead Digital Design Engineer Texas Instruments Dallas, TX

synchronous digital skills. • Verilog or VHDL RTL development experience • Simulation ... Knowledge of System verilog, constrained random and assertion based verification... more

Oct 10 Lead Electrical / System Engineer GE Billerica, MA

The product development team is seeking an experienced Lead Electrical / System Engineer t ... Familiarity with FPGA design including Verilog/System Verilog Familiarity with... more

Oct 08 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

implementing, debugging, and closing SystemVerilog functional coverage groups. ... experience Candidate SHOULD also have system verilog test bench experience. We need... more

Oct 08 Pre Silicon Verification Engineer Sage IT Hudson, MA

using System Verilog UVM, Good experience in System Verilog –UVM based verification environment development, Sound understanding of Random and constrained random-verification... more

Oct 08 PDG - Peripheral Connectivity Hub Engineer Intern (MS/PhD Level) 2014/2015 Intel Folsom, CA

FPGA codes -Familiar with Systemverilog Job assignments are usually for ... Qualifications: - Experience with system verilog/verilog/VHDL etc. - Experience with... more

Oct 06 Senior Staff Digital Design Engineer Fusion408 San Jose, CA

* Architecture of Digital Filters * RTL Design using Verilog/System Verilog * Top-level Synthesis &Static Timing Analysis (STA) * Digital Design for Ultra-Low Power applications *... more

Oct 06 Digital Design Engineer Fusion408 Westlake Village, CA

level integration and verification using Verilog and system Verilog, synthesis and ... processing products. * Solid knowledge in Verilog and system Verilog * Solid knowledge... more

Oct 02 Principal Engineer Leading Manufacturer of Computer Hardware Santa Clara, CA

of architectural specification documents, system level models, complex circuit design, ... with the VCS, Vera verification language, System Verilog, objected-oriented... more

Sep 30 Contract Staff Design Engineer Horizontal Integration San Jose, CA

of logic fundamentals Excellent knowledge of Verilog Capable of writing ... Good knowledge of verification methodology System Verilog experience Horizontal... more

Sep 23 Functional Verification Engineer - Pre-Silicon: 234296 Core-tech Santa Clara, CA

System Verilog OVM/UVMc. Good experience in System Verilog - OVM/UVM based verification ... architectureb. Creating test scenarios(System Verilog OVM)c. Work with RTL teams to... more

Sep 22 SoC Verification Engineers Calsoftlabs Raleigh, NC

have experience in System Verilog and either UVM (preferred) or OVM. 3+ years of ... chip, sub-system and/or blocks. You will define chip level verification strategies,... more

Sep 17 New Grad - ASIC Design Engineer Viasat Cleveland, OH

logic designs with System Verilog • Experience in the design and verification of ... design verification of Verilog code in satellite and optical communications equipment. You... more

Sep 16 Principal ASIC Design Engineer Fortinet Technologies Sunnyvale, CA

Altera/Xilinx FPGA;· Participating system/board level bring up, debugging and ... knowledge;· Knowledge of System Verilog and UVM verification methodology;· Highly... more

Sep 11 Intern: ASIC Engineer Juniper Networks Sunnyvale, CA

or Computer Science * Strong Verilog, SystemC or C/C++, Perl/shell skills. * ... Perl or Python scripting experience. * System Verilog would be a plus but not necessary... more

Sep 10 R&D Engineer, Staff Synopsys Hillsboro, OR

to Verilog/VHDL. · Exposure to System Verilog, UVM, VMM or OVM · Knowledge of IC Design flows. · Unix, Perl and Tcl Scripting Knowledge. · Knowledge of SATA/PCIE protocol would be... more

Sep 09 C++ and System Verilog/UVM Engineer Hire IT People Marlborough, MA

Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. more

Sep 06 Electrical Engineer Sr Lockheed Martin Orlando, FL

skills. Familiarity with video system design, synchronization, image ... Experience with Verilog, C/C++, MathLab/Simulink, System Verilog languages; Synopsis Synpl... more

Sep 05 Senior Engineer, FPGA Design CSR Cambridge, MA

HW background · Proficient in System Verilog · Competent in digital design for ... equivalent qualification) · System and architectural design · Writing of design... more

Aug 29 Entry Level Digital Design Engineer Cirrus Logic Austin, TX

Primary activities include: design using Verilog, logic simulation, functional ... and Sate Machines Strong Skills System Verilog Applied to Functional... more

Aug 14 ASIC Developer Braves Technologies Irvine, CA

tes who are CAP Exempt and have a valid stamped H1B visa shouldapply.Location: Irvine CA. ASIC DeveloperSkills Required: ASIC Must have experience in System Verilog/ Verilog,OVM,... more

Aug 14 Engineer, Digital IC Design Marvell Technology Group Santa Clara, CA

to tape-out . Familiar with ARM SOC embeded system and AMBA. . Understanding of DDR, ... and NVMe would be a plus. . Understanding of System Verilog would be a plus . more

Aug 05 Design Modeling Engineer-Temporary - Engineer III Mindlance San Diego, CA

knowledge of HVLs( System Verilog ), HDLs ( Verilog/VHDL/SystemVerilog), C/C++, SystemC ... - Verilog, system Verilog or vhdl - Experience in ASIC/System verification, processor veri... more

Aug 05 Senior Member Technical Staff Mentor Graphics Indiana

verification • Required: Strong Verilog/System Verilog Experience, Strong C++ PLI experience, Good Assembly understanding, Some bus protocol understanding ( e.g. PCI, AXI ) •... more

Aug 04 Design Modeling Engineer Calsoftlabs-an Alten Group Company San Diego, CA

video standards and video codec protocols -System C TLM 2.0 experience -Design and ... AutoESL, Forte, etc. -Verilog, system Verilog or vhdl Responsibilities:... more

Jul 14 DFX validation engineer Intel Israel, PR

validation environments based on System Verilog and work with RTLdesigners and post ... verification/validation methods, Specman language, SystemVerilog, DFX design &... more

Jul 01 IC Design Verficiation Engineer Avago Technologies Allentown, PA

processor products. The candidate will use SystemVerilog, Verilog and other Unix ... using behavioral simulation using System Verilog, VMM or UVM methodologies. *... more

Jun 30 Digital Design Engineer Inphi Thousand Oaks, CA

implementing RTL designs using Verilog/SystemVerilog; implementing verification test ... of digital and mixed-signal circuits; Verilog or System Verilog to verify functional... more

Jun 20 Design Verification Engineer 2 AMD Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 17 FPGA Engineer III - Bothell Sonosite Washington

(VHDL, System Verilog, System C or C/C , scripting in Bash, Python, Perl, or Tcl). ��� Experience with ISO, FDA, or other regulated product development environments is a plus. ���... more

Jun 13 Design Verification Engineer 2 Amd | Seamicro Austin, TX

OO Programming • Experience with Verilog / System Verilog, UVM • Strong working ... function • Debug of Verilog RTL and gate-level simulation, at the IP and/or... more

Jun 09 Sr Staff Engineer Seagate Minnesota

utilizing Unix, Linux, Synopsys Tools, and Verilog. Experience running large scale ... Experience designing in Verilog and/or System Verilog... more

Jun 06 Memory Subsystem Design Engineer Talarience Folsom, CA

and/or software architects to develop system models, evaluate memory system ... models and evaluation tools in C/C++, system Verilog and similar environments. more

May 31 Engineer, ASIC Design Verification Results Center Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 30 Engineer, ASIC Design Verification Marvell Santa Clara, CA

verification tests for HDD using C, System Verilog in Unix environments. Need to understand real time SOC concepts and programming. Knowledge about industrial standard interfaces... more

May 20 IC Verification Engineer eTech Hi Simi Valley, CA

candidate will have experience using System Verilog, Specman e, Vera or System C) ... * Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.If interested... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired ... a plus. Knowledge of ARM microprocessor-system is a big plus. Very strong... more

Apr 07 Principal Application Engineer Cadence Design Systems Austin, TX

e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience ... Languages: SystemVerilog, Specman e, VHDL, verilog Methodologies: Preferable experience in... more

Mar 25 DV -SoC Design Verification OVM/UVM Recruiting Engine (mls) San Diego, CA

not apply if you do not have experience in System Verilog and either UVM (preferred) or ... You will be contributing to the verification effort of a complex chip, sub-system and/or b... more

Mar 24 Digital Design Engineer Google Mountain View, CA

the lowest levels of circuit design to large system design and see those systems all the ... * Proficient in RTL / Logic / Verilog / System Verilog. * Successfully delivered... more

Feb 24 SoC Design Verification Engineer Altera Austin, TX

to the following: Developing unit/core/system level testbench, BFMs (Bus Functional ... methodologies (such as UVM, OVM, System Verilog, constrained-random stimulus... more

Feb 13 Principal Verification Engineer Aba Search San Jose, CA

and development and modeling using UVM, SystemVerilog, Verilog. EXPERIENCE o ... verification languages OVM/UVM/System Verilog/C++ o Expertise in putting... more

Feb 12 Design Verification Engineer Commnexus Santa Clara, CA

programming ability in C, C++, System C and System Verilog Knowledge in CPU verification Must be a highly organized, detail-oriented self-starter, who works well independently, as... more

Feb 05 Video Codec Engineer Extron Electronics Raleigh, NC

* Experience in C/C++, Verilog/VHDL, System Verilog/C, Perl/Python ... and manufacturer of professional AV system products. Extron products are used to... more

Jan 08 Sr. R&D Engineer Real Intent California

of the following fields: GUI, Verilog/System Verilog/VHDL Compilation, Synthesis ... and verification flow, working knowledge of Verilog, VHDL, and SystemVerilog... more

Jan 07 ASIC Verification Engineer Systel Santa Clara, CA

VMM, OVM, UVM Development will be done System Verilog Develop test plans, execute and ... building Verification environments using SystemVerilog, VMM/OVM/UVM Past experience in... more

Jan 07 Senior Verification Engineer Aba Search San Jose, CA

o Hardware modeling using UVM, Verilog, System Verilog or C/C++ o 6 + years of ... functional coverage o Expertise in System Verilog, OVM/UVM or Vera based tools o... more

Dec 31 FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL Darwin Recruitment Newport Beach, CA

FPGA/ASIC Designer - Cadence, Verilog, Specman, VHDL FPGA/ASIC Designer - Darwin Recruitme ... or equivalent academic qualification. System Verilog or Specman Cadence E... more

Dec 02 Electrical Design Engineer Cypress Semiconductor San Jose, CA

knowledge of Verilog HDL for synthesis and modeling • Good skills in a programming ... formal verification • System Verilog • Gate level verification with timing Cypress is... more

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